Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9781275 [patent_doc_number] => 08856496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Microprocessor that fuses load-alu-store and JCC macroinstructions' [patent_app_type] => utility [patent_app_number] => 13/034808 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13034808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/034808
Microprocessor that fuses load-alu-store and JCC macroinstructions Feb 24, 2011 Issued
Array ( [id] => 8149267 [patent_doc_number] => 08166280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Microprocessor for executing byte compiled JAVA code' [patent_app_type] => utility [patent_app_number] => 13/030984 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166280.pdf [firstpage_image] =>[orig_patent_app_number] => 13030984 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/030984
Microprocessor for executing byte compiled JAVA code Feb 17, 2011 Issued
Array ( [id] => 4606360 [patent_doc_number] => 07987346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Method and apparatus for assigning thread priority in a processor or the like' [patent_app_type] => utility [patent_app_number] => 13/011711 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3481 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987346.pdf [firstpage_image] =>[orig_patent_app_number] => 13011711 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011711
Method and apparatus for assigning thread priority in a processor or the like Jan 20, 2011 Issued
Array ( [id] => 6057361 [patent_doc_number] => 20110113217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'GENERATE PREDICTES INSTRUCTION FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/006243 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 38247 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113217.pdf [firstpage_image] =>[orig_patent_app_number] => 13006243 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006243
Generate predicates instruction for processing vectors Jan 12, 2011 Issued
Array ( [id] => 10841190 [patent_doc_number] => 08868889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Instruction breakpoints in a multi-core, multi-thread network communications processor architecture' [patent_app_type] => utility [patent_app_number] => 12/976045 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15726 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12976045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976045
Instruction breakpoints in a multi-core, multi-thread network communications processor architecture Dec 21, 2010 Issued
Array ( [id] => 9885912 [patent_doc_number] => 08972698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Vector conflict instructions' [patent_app_type] => utility [patent_app_number] => 12/976616 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5341 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12976616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976616
Vector conflict instructions Dec 21, 2010 Issued
Array ( [id] => 8267348 [patent_doc_number] => 20120166777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD AND APPARATUS FOR SWITCHING THREADS' [patent_app_type] => utility [patent_app_number] => 12/976034 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1934 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12976034 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976034
METHOD AND APPARATUS FOR SWITCHING THREADS Dec 21, 2010 Abandoned
Array ( [id] => 9611608 [patent_doc_number] => 08788797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Combined level 1 and level 2 branch predictor' [patent_app_type] => utility [patent_app_number] => 12/975686 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4539 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975686 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975686
Combined level 1 and level 2 branch predictor Dec 21, 2010 Issued
Array ( [id] => 9829368 [patent_doc_number] => 08938606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'System, apparatus, and method for segment register read and write regardless of privilege level' [patent_app_type] => utility [patent_app_number] => 12/976981 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5535 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12976981 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976981
System, apparatus, and method for segment register read and write regardless of privilege level Dec 21, 2010 Issued
Array ( [id] => 8242464 [patent_doc_number] => 20120151184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'HARD OBJECT: CONSTRAINING CONTROL FLOW AND PROVIDING LIGHTWEIGHT KERNEL CROSSINGS' [patent_app_type] => utility [patent_app_number] => 12/965158 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 27239 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965158 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965158
HARD OBJECT: CONSTRAINING CONTROL FLOW AND PROVIDING LIGHTWEIGHT KERNEL CROSSINGS Dec 9, 2010 Abandoned
Array ( [id] => 8242447 [patent_doc_number] => 20120151183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS' [patent_app_type] => utility [patent_app_number] => 12/963298 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7390 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963298
Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers Dec 7, 2010 Issued
Array ( [id] => 6073604 [patent_doc_number] => 20110047361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Load/Move Duplicate Instructions for a Processor' [patent_app_type] => utility [patent_app_number] => 12/940782 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4454 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047361.pdf [firstpage_image] =>[orig_patent_app_number] => 12940782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/940782
Load/move duplicate instructions for a processor Nov 4, 2010 Issued
Array ( [id] => 8923908 [patent_doc_number] => 08489857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Processor cluster architecture and associated parallel processing methods' [patent_app_type] => utility [patent_app_number] => 12/940799 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6004 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12940799 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/940799
Processor cluster architecture and associated parallel processing methods Nov 4, 2010 Issued
Array ( [id] => 7706239 [patent_doc_number] => 08090932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-03 [patent_title] => 'Communication bus with hidden pre-fetch registers' [patent_app_type] => utility [patent_app_number] => 12/917426 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/090/08090932.pdf [firstpage_image] =>[orig_patent_app_number] => 12917426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/917426
Communication bus with hidden pre-fetch registers Oct 31, 2010 Issued
Array ( [id] => 8143389 [patent_doc_number] => 20120096241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams' [patent_app_type] => utility [patent_app_number] => 12/905208 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096241.pdf [firstpage_image] =>[orig_patent_app_number] => 12905208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/905208
Performance of emerging applications in a virtualized environment using transient instruction streams Oct 14, 2010 Issued
Array ( [id] => 8143381 [patent_doc_number] => 20120096240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware' [patent_app_type] => utility [patent_app_number] => 12/905176 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096240.pdf [firstpage_image] =>[orig_patent_app_number] => 12905176 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/905176
Managing migration of a prefetch stream from one processor core to another processor core Oct 14, 2010 Issued
Array ( [id] => 6217622 [patent_doc_number] => 20110138156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'METHOD AND APPARATUS FOR EVALUATING A LOGICAL EXPRESSION AND PROCESSOR MAKING USE OF SAME' [patent_app_type] => utility [patent_app_number] => 12/905753 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9106 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138156.pdf [firstpage_image] =>[orig_patent_app_number] => 12905753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/905753
METHOD AND APPARATUS FOR EVALUATING A LOGICAL EXPRESSION AND PROCESSOR MAKING USE OF SAME Oct 14, 2010 Abandoned
Array ( [id] => 8143387 [patent_doc_number] => 20120096242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Method and Apparatus for Performing Control of Flow in a Graphics Processor Architecture' [patent_app_type] => utility [patent_app_number] => 12/904199 [patent_app_country] => US [patent_app_date] => 2010-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096242.pdf [firstpage_image] =>[orig_patent_app_number] => 12904199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/904199
Method and apparatus for performing control of flow in a graphics processor architecture Oct 13, 2010 Issued
Array ( [id] => 9314907 [patent_doc_number] => 08656142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Managing multiple speculative assist threads at differing cache levels' [patent_app_type] => utility [patent_app_number] => 12/903620 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903620 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903620
Managing multiple speculative assist threads at differing cache levels Oct 12, 2010 Issued
Array ( [id] => 8130535 [patent_doc_number] => 20120089815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'DETERMINING PROCESSOR OFFSETS TO SYNCHRONIZE PROCESSOR TIME VALUES' [patent_app_type] => utility [patent_app_number] => 12/902047 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5056 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20120089815.pdf [firstpage_image] =>[orig_patent_app_number] => 12902047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/902047
Determining processor offsets to synchronize processor time values Oct 10, 2010 Issued
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