Benjamin P. Geib

Array ( [id] => 8752073 [patent_doc_number] => 08417917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Processor core stacking for efficient collaboration' [patent_app_type] => utility [patent_app_number] => 12/570351 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8998095 [patent_doc_number] => 08522000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Trap handler architecture for a parallel processing unit' [patent_app_type] => utility [patent_app_number] => 12/569831 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12569831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6387861 [patent_doc_number] => 20100082943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'DYNAMIC RECONFIGURATION SUPPORT APPARATUS, DYNAMIC RECONFIGURATION SUPPORT METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/565471 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12813 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082943.pdf [firstpage_image] =>[orig_patent_app_number] => 12565471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6031487 [patent_doc_number] => 20110055523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'EARLY BRANCH DETERMINATION' [patent_app_type] => utility [patent_app_number] => 12/551240 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055523.pdf [firstpage_image] =>[orig_patent_app_number] => 12551240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6646677 [patent_doc_number] => 20100174886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Multi-Core Processing Utilizing Prioritized Interrupts for Optimization' [patent_app_type] => utility [patent_app_number] => 12/550951 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4671 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174886.pdf [firstpage_image] =>[orig_patent_app_number] => 12550951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10556142 [patent_doc_number] => 09280343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Store queue with token to facilitate efficient thread synchronization' [patent_app_type] => utility [patent_app_number] => 12/538717 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12538717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7681104 [patent_doc_number] => 20100023704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'VIRTUALIZABLE ADVANCED SYNCHRONIZATION FACILITY' [patent_app_type] => utility [patent_app_number] => 12/510905 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023704.pdf [firstpage_image] =>[orig_patent_app_number] => 12510905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7681105 [patent_doc_number] => 20100023703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'HARDWARE TRANSACTIONAL MEMORY SUPPORT FOR PROTECTED AND UNPROTECTED SHARED-MEMORY ACCESSES IN A SPECULATIVE SECTION' [patent_app_type] => utility [patent_app_number] => 12/510884 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023703.pdf [firstpage_image] =>[orig_patent_app_number] => 12510884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7681101 [patent_doc_number] => 20100023707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'PROCESSOR WITH SUPPORT FOR NESTED SPECULATIVE SECTIONS WITH DIFFERENT TRANSACTIONAL MODES' [patent_app_type] => utility [patent_app_number] => 12/510856 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023707.pdf [firstpage_image] =>[orig_patent_app_number] => 12510856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7681102 [patent_doc_number] => 20100023706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'COEXISTENCE OF ADVANCED HARDWARE SYNCHRONIZATION AND GLOBAL LOCKS' [patent_app_type] => utility [patent_app_number] => 12/510893 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023706.pdf [firstpage_image] =>[orig_patent_app_number] => 12510893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4572763 [patent_doc_number] => 07962733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Branch prediction mechanisms using multiple hash functions' [patent_app_type] => utility [patent_app_number] => 12/493768 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962733.pdf [firstpage_image] =>[orig_patent_app_number] => 12493768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5399693 [patent_doc_number] => 20090319756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Duplexed operation processor control system, and duplexed operation processor control method' [patent_app_type] => utility [patent_app_number] => 12/457682 [patent_app_country] => US [patent_app_date] => 2009-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4247 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319756.pdf [firstpage_image] =>[orig_patent_app_number] => 12457682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11523409 [patent_doc_number] => 09606807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Direct communication with a processor internal to a memory device' [patent_app_type] => utility [patent_app_number] => 12/478450 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12478450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9781270 [patent_doc_number] => 08856492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Method for vector processing' [patent_app_type] => utility [patent_app_number] => 12/995322 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4188 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12995322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5553921 [patent_doc_number] => 20090287907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'System for providing trace data in a data processor having a pipelined architecture' [patent_app_type] => utility [patent_app_number] => 12/387152 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8420 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20090287907.pdf [firstpage_image] =>[orig_patent_app_number] => 12387152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8273105 [patent_doc_number] => 08214626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Method and apparatus for shuffling data' [patent_app_type] => utility [patent_app_number] => 12/387958 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 20223 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12387958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8010823 [patent_doc_number] => 08086829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Method and apparatus for processing data related to handling interrupts in data processing' [patent_app_type] => utility [patent_app_number] => 12/379970 [patent_app_country] => US [patent_app_date] => 2009-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 77 [patent_no_of_words] => 41299 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086829.pdf [firstpage_image] =>[orig_patent_app_number] => 12379970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5356406 [patent_doc_number] => 20090187750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Binary Translator with Precise Exception Synchronization Mechanism' [patent_app_type] => utility [patent_app_number] => 12/398655 [patent_app_country] => US [patent_app_date] => 2009-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14792 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187750.pdf [firstpage_image] =>[orig_patent_app_number] => 12398655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9879191 [patent_doc_number] => 08966489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Information processing device, information processing method, and computer product' [patent_app_type] => utility [patent_app_number] => 12/393601 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9364 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12393601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9940969 [patent_doc_number] => 08990801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Server switch integration in a virtualized system' [patent_app_type] => utility [patent_app_number] => 12/362876 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12362876 [rel_patent_id] =>[rel_patent_doc_number] =>)