Search

Benjamin P. Geib

Examiner (ID: 5552, Phone: (571)272-8628 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181, 2123
Total Applications
703
Issued Applications
612
Pending Applications
6
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4780749 [patent_doc_number] => 20080288748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Dynamic core switching' [patent_app_type] => utility [patent_app_number] => 12/215760 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 23647 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288748.pdf [firstpage_image] =>[orig_patent_app_number] => 12215760 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215760
Dynamic core switching Jun 29, 2008 Issued
Array ( [id] => 8971707 [patent_doc_number] => 08510535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Mixed torus and hypercube multi-rank tensor expansion method' [patent_app_type] => utility [patent_app_number] => 12/141983 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2315 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12141983 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141983
Mixed torus and hypercube multi-rank tensor expansion method Jun 18, 2008 Issued
Array ( [id] => 4508170 [patent_doc_number] => 07958334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method and apparatus for an efficient multi-path trace cache design' [patent_app_type] => utility [patent_app_number] => 12/131418 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4299 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958334.pdf [firstpage_image] =>[orig_patent_app_number] => 12131418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131418
Method and apparatus for an efficient multi-path trace cache design Jun 1, 2008 Issued
Array ( [id] => 5553899 [patent_doc_number] => 20090287885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Administering Non-Cacheable Memory Load Instructions' [patent_app_type] => utility [patent_app_number] => 12/121222 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20090287885.pdf [firstpage_image] =>[orig_patent_app_number] => 12121222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121222
Administering non-cacheable memory load instructions May 14, 2008 Issued
Array ( [id] => 5467451 [patent_doc_number] => 20090327651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Information Handling System Including A Multiple Compute Element Processor With Distributed Data On-Ramp Data-Off Ramp Topology' [patent_app_type] => utility [patent_app_number] => 12/112780 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327651.pdf [firstpage_image] =>[orig_patent_app_number] => 12112780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112780
Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology Apr 29, 2008 Issued
Array ( [id] => 4447453 [patent_doc_number] => 07930525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method and apparatus for an efficient multi-path trace cache design' [patent_app_type] => utility [patent_app_number] => 12/110745 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4250 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930525.pdf [firstpage_image] =>[orig_patent_app_number] => 12110745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110745
Method and apparatus for an efficient multi-path trace cache design Apr 27, 2008 Issued
Array ( [id] => 4581433 [patent_doc_number] => 07840780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Shared resources in a chip multiprocessor' [patent_app_type] => utility [patent_app_number] => 12/098303 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840780.pdf [firstpage_image] =>[orig_patent_app_number] => 12098303 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/098303
Shared resources in a chip multiprocessor Apr 3, 2008 Issued
Array ( [id] => 6633899 [patent_doc_number] => 20100325389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'Microprocessor communications system' [patent_app_type] => utility [patent_app_number] => 12/080826 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13740 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325389.pdf [firstpage_image] =>[orig_patent_app_number] => 12080826 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/080826
Microprocessor communications system Apr 3, 2008 Abandoned
Array ( [id] => 10194665 [patent_doc_number] => 09223575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Processor exploiting trivial arithmetic operations' [patent_app_type] => utility [patent_app_number] => 12/531408 [patent_app_country] => US [patent_app_date] => 2008-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12531408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/531408
Processor exploiting trivial arithmetic operations Mar 15, 2008 Issued
Array ( [id] => 5381394 [patent_doc_number] => 20090193233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode' [patent_app_type] => utility [patent_app_number] => 12/043747 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4622 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193233.pdf [firstpage_image] =>[orig_patent_app_number] => 12043747 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043747
Mechanism for avoiding check stops in speculative accesses while operating in real mode Mar 5, 2008 Issued
Array ( [id] => 7768157 [patent_doc_number] => 08117423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-14 [patent_title] => 'Pipeline replay support for multicycle operations' [patent_app_type] => utility [patent_app_number] => 12/042224 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117423.pdf [firstpage_image] =>[orig_patent_app_number] => 12042224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042224
Pipeline replay support for multicycle operations Mar 3, 2008 Issued
Array ( [id] => 4700155 [patent_doc_number] => 20080222339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Processor architecture with switch matrices for transferring data along buses' [patent_app_type] => utility [patent_app_number] => 12/070790 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7040 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222339.pdf [firstpage_image] =>[orig_patent_app_number] => 12070790 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/070790
Processor architecture with switch matrices for transferring data along buses Feb 20, 2008 Issued
Array ( [id] => 4829961 [patent_doc_number] => 20080126757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Cellular engine for a data processing system' [patent_app_type] => utility [patent_app_number] => 12/004120 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126757.pdf [firstpage_image] =>[orig_patent_app_number] => 12004120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004120
Cellular engine for a data processing system Dec 18, 2007 Issued
Array ( [id] => 4881848 [patent_doc_number] => 20080155231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHOD AND DATA PROCESSING SYSTEM FOR PROCESSOR-TO-PROCESSOR COMMUNICATION IN A CLUSTERED MULTI-PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/954686 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7059 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155231.pdf [firstpage_image] =>[orig_patent_app_number] => 11954686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954686
Method and data processing system for processor-to-processor communication in a clustered multi-processor system Dec 11, 2007 Issued
Array ( [id] => 4558810 [patent_doc_number] => 07877580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Branch lookahead prefetch for microprocessors' [patent_app_type] => utility [patent_app_number] => 11/953799 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6075 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877580.pdf [firstpage_image] =>[orig_patent_app_number] => 11953799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953799
Branch lookahead prefetch for microprocessors Dec 9, 2007 Issued
Array ( [id] => 7768049 [patent_doc_number] => 08117364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Enhanced protocol and architecture for low bandwidth force feedback game controller' [patent_app_type] => utility [patent_app_number] => 11/939218 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13230 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117364.pdf [firstpage_image] =>[orig_patent_app_number] => 11939218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939218
Enhanced protocol and architecture for low bandwidth force feedback game controller Nov 12, 2007 Issued
Array ( [id] => 4448947 [patent_doc_number] => 07865699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code' [patent_app_type] => utility [patent_app_number] => 11/931815 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5171 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865699.pdf [firstpage_image] =>[orig_patent_app_number] => 11931815 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/931815
Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code Oct 30, 2007 Issued
Array ( [id] => 4798857 [patent_doc_number] => 20080010443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'System and method for executing conditional branch instructions in a data processor' [patent_app_type] => utility [patent_app_number] => 11/900978 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7100 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010443.pdf [firstpage_image] =>[orig_patent_app_number] => 11900978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/900978
System and method for reducing power consumption in a data processor having a clustered architecture Sep 13, 2007 Issued
Array ( [id] => 68917 [patent_doc_number] => 07761688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Multiple thread in-order issue in-order completion DSP and micro-controller' [patent_app_type] => utility [patent_app_number] => 11/899557 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5383 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761688.pdf [firstpage_image] =>[orig_patent_app_number] => 11899557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/899557
Multiple thread in-order issue in-order completion DSP and micro-controller Sep 5, 2007 Issued
Array ( [id] => 87663 [patent_doc_number] => 07743237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Register file bit and method for fast context switch' [patent_app_type] => utility [patent_app_number] => 11/848498 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2367 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743237.pdf [firstpage_image] =>[orig_patent_app_number] => 11848498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848498
Register file bit and method for fast context switch Aug 30, 2007 Issued
Menu