Search

Benyam Haile

Examiner (ID: 2511, Phone: (571)272-2080 , Office: P/2686 )

Most Active Art Unit
2688
Art Unit(s)
2681, 2688, 2686
Total Applications
715
Issued Applications
415
Pending Applications
88
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11671848 [patent_doc_number] => 20170160569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'ARRAY SUBSTRATE HAVING CONDUCTIVE PLANAR LAYER AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/117556 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7086 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15117556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/117556
ARRAY SUBSTRATE HAVING CONDUCTIVE PLANAR LAYER AND METHOD OF MANUFACTURING THE SAME Dec 10, 2015 Abandoned
Array ( [id] => 11346253 [patent_doc_number] => 09530669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity' [patent_app_type] => utility [patent_app_number] => 14/954051 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3595 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/954051
Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity Nov 29, 2015 Issued
Array ( [id] => 10718334 [patent_doc_number] => 20160064480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'Semiconductor Constructions, Memory Arrays and Electronic Systems' [patent_app_type] => utility [patent_app_number] => 14/935049 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6418 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935049
Semiconductor Constructions, Memory Arrays and Electronic Systems Nov 5, 2015 Abandoned
Array ( [id] => 11592829 [patent_doc_number] => 20170117241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER' [patent_app_type] => utility [patent_app_number] => 14/920197 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920197
MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER Oct 21, 2015 Abandoned
Array ( [id] => 11952441 [patent_doc_number] => 20170256592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'RADIATION-EMITTING APPARATUS AND METHOD FOR PRODUCING SAME' [patent_app_type] => utility [patent_app_number] => 15/509153 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15509153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/509153
Radiation-emitting apparatus having an outer optoelectronic device surrounding an inner optoelectronic device and methods for producing the same Sep 2, 2015 Issued
Array ( [id] => 10486932 [patent_doc_number] => 20150371952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SEMICONDUCTOR CONTACT WITH DIFFUSION-CONTROLLED IN SITU INSULATOR FORMATION' [patent_app_type] => utility [patent_app_number] => 14/842336 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8420 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842336
SEMICONDUCTOR CONTACT WITH DIFFUSION-CONTROLLED IN SITU INSULATOR FORMATION Aug 31, 2015 Abandoned
Array ( [id] => 10472304 [patent_doc_number] => 20150357320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Method of Forming Package-On-Package (PoP) Structure' [patent_app_type] => utility [patent_app_number] => 14/828244 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 5705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828244
Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon Aug 16, 2015 Issued
Array ( [id] => 11021368 [patent_doc_number] => 20160218323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/827254 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5543 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827254
ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 13, 2015 Abandoned
Array ( [id] => 13111853 [patent_doc_number] => 10074584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer [patent_app_type] => utility [patent_app_number] => 14/821576 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2416 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/821576
Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer Aug 6, 2015 Issued
Array ( [id] => 11883985 [patent_doc_number] => 09755171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Organic light-emitting diode including an interlayer to maintain a hole-electron balance in the emitting layer and display panel including the same' [patent_app_type] => utility [patent_app_number] => 14/803551 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/803551
Organic light-emitting diode including an interlayer to maintain a hole-electron balance in the emitting layer and display panel including the same Jul 19, 2015 Issued
Array ( [id] => 11353656 [patent_doc_number] => 20160372396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'CHIP PACKAGES WITH REDUCED TEMPERATURE VARIATION' [patent_app_type] => utility [patent_app_number] => 14/745800 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745800
CHIP PACKAGES WITH REDUCED TEMPERATURE VARIATION Jun 21, 2015 Abandoned
Array ( [id] => 10487206 [patent_doc_number] => 20150372226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'VARIABLE SELECTIVITY SILICON GROWTH PROCESS' [patent_app_type] => utility [patent_app_number] => 14/743132 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743132
VARIABLE SELECTIVITY SILICON GROWTH PROCESS Jun 17, 2015 Abandoned
Array ( [id] => 11353673 [patent_doc_number] => 20160372413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME' [patent_app_type] => utility [patent_app_number] => 14/741636 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5085 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741636
UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME Jun 16, 2015 Abandoned
Array ( [id] => 11353620 [patent_doc_number] => 20160372360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/742550 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742550
SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION Jun 16, 2015 Abandoned
Array ( [id] => 10378245 [patent_doc_number] => 20150263252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICES' [patent_app_type] => utility [patent_app_number] => 14/727810 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727810
OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICES May 31, 2015 Abandoned
Array ( [id] => 10463825 [patent_doc_number] => 20150348840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHODS OF FILLING HIGH ASPECT RATIO FEATURES WITH FLUORINE FREE TUNGSTEN' [patent_app_type] => utility [patent_app_number] => 14/723353 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9802 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723353 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723353
METHODS OF FILLING HIGH ASPECT RATIO FEATURES WITH FLUORINE FREE TUNGSTEN May 26, 2015 Abandoned
Array ( [id] => 10718278 [patent_doc_number] => 20160064425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/721505 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7455 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721505 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721505
Thin film transistor array substrate having a gate electrode comprising two conductive layers May 25, 2015 Issued
Array ( [id] => 10370276 [patent_doc_number] => 20150255281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SILICON SUBSTRATE PREPARATION FOR SELECTIVE III-V EPITAXY' [patent_app_type] => utility [patent_app_number] => 14/720427 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3877 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/720427
SILICON SUBSTRATE PREPARATION FOR SELECTIVE III-V EPITAXY May 21, 2015 Abandoned
Array ( [id] => 11746699 [patent_doc_number] => 20170200772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SUBSTRATE AND METHOD OF MANUFACTURING PANEL' [patent_app_type] => utility [patent_app_number] => 15/313044 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15313044 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/313044
SUBSTRATE AND METHOD OF MANUFACTURING PANEL May 21, 2015 Abandoned
Array ( [id] => 11043724 [patent_doc_number] => 20160240680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SILICON AND GERMANIUM MATERIAL FILLING A CAVITY REGION COMPRISING A NOTCH REGION FORMED WITHIN A SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/691511 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3575 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691511
SEMICONDUCTOR DEVICE HAVING A SILICON AND GERMANIUM MATERIAL FILLING A CAVITY REGION COMPRISING A NOTCH REGION FORMED WITHIN A SEMICONDUCTOR SUBSTRATE Apr 19, 2015 Abandoned
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