Search

Bernard E. Cothran

Examiner (ID: 8276, Phone: (571)270-5594 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2188, 2147, 2123, 2128
Total Applications
415
Issued Applications
168
Pending Applications
62
Abandoned Applications
197

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4720948 [patent_doc_number] => 20080243471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => ' SYSTEM AND A METHOD FOR CHECKING LOCK-STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER' [patent_app_type] => utility [patent_app_number] => 12/136557 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20080243471.pdf [firstpage_image] =>[orig_patent_app_number] => 12136557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136557
System and a method for checking lock-step consistency between an in circuit emulation and a microcontroller Jun 9, 2008 Issued
Array ( [id] => 7992285 [patent_doc_number] => 08078448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Systems and methods for automated testing' [patent_app_type] => utility [patent_app_number] => 12/127570 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078448.pdf [firstpage_image] =>[orig_patent_app_number] => 12127570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127570
Systems and methods for automated testing May 26, 2008 Issued
Array ( [id] => 5553482 [patent_doc_number] => 20090287468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'EVENT-DRIVEN EMULATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/120895 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20090287468.pdf [firstpage_image] =>[orig_patent_app_number] => 12120895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/120895
Event-driven emulation system May 14, 2008 Issued
Array ( [id] => 8366122 [patent_doc_number] => 08255199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Characterizing performance of an electronic system' [patent_app_type] => utility [patent_app_number] => 12/120894 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5571 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12120894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/120894
Characterizing performance of an electronic system May 14, 2008 Issued
Array ( [id] => 4780223 [patent_doc_number] => 20080288221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING ANALYSIS MESH' [patent_app_type] => utility [patent_app_number] => 12/119978 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4559 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288221.pdf [firstpage_image] =>[orig_patent_app_number] => 12119978 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119978
METHOD AND APPARATUS FOR GENERATING ANALYSIS MESH May 12, 2008 Abandoned
Array ( [id] => 10840703 [patent_doc_number] => 08868400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Modeling storage environments' [patent_app_type] => utility [patent_app_number] => 12/112000 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6437 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12112000 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112000
Modeling storage environments Apr 29, 2008 Issued
Array ( [id] => 8366125 [patent_doc_number] => 08255203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method of debugging an executable computer program having instructions for different computer architectures' [patent_app_type] => utility [patent_app_number] => 12/109269 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12109269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109269
Method of debugging an executable computer program having instructions for different computer architectures Apr 23, 2008 Issued
Array ( [id] => 5387068 [patent_doc_number] => 20090228313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'METHOD AND SYSTEM FOR DETERMINING SERVICE AREA OF SUPPLY CHAIN BY SIMULATING SERVICE CYCLE TIME' [patent_app_type] => utility [patent_app_number] => 12/043540 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228313.pdf [firstpage_image] =>[orig_patent_app_number] => 12043540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043540
Method and system for determining service area of supply chain by simulating service cycle time Mar 5, 2008 Issued
Array ( [id] => 4699657 [patent_doc_number] => 20080221841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHOD AND RECORDING MEDIA' [patent_app_type] => utility [patent_app_number] => 12/041901 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5781 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20080221841.pdf [firstpage_image] =>[orig_patent_app_number] => 12041901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041901
METHOD AND RECORDING MEDIA Mar 3, 2008 Abandoned
Array ( [id] => 5541012 [patent_doc_number] => 20090222817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Navigation in Simulated Workflows' [patent_app_type] => utility [patent_app_number] => 12/040704 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20090222817.pdf [firstpage_image] =>[orig_patent_app_number] => 12040704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040704
Navigation in simulated workflows Feb 28, 2008 Issued
Array ( [id] => 9129694 [patent_doc_number] => 08577650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'User interface for modeling thermal comfort' [patent_app_type] => utility [patent_app_number] => 12/037828 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15422 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12037828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037828
User interface for modeling thermal comfort Feb 25, 2008 Issued
Array ( [id] => 8032747 [patent_doc_number] => 08145467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Method and apparatus for profiling a hardware/software embedded system' [patent_app_type] => utility [patent_app_number] => 12/036920 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6350 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/145/08145467.pdf [firstpage_image] =>[orig_patent_app_number] => 12036920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036920
Method and apparatus for profiling a hardware/software embedded system Feb 24, 2008 Issued
Array ( [id] => 5393368 [patent_doc_number] => 20090210681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Method and Apparatus of Handling Instruction Rejects, Partial Rejects, Stalls and Branch Wrong in a Simulation Model' [patent_app_type] => utility [patent_app_number] => 12/032647 [patent_app_country] => US [patent_app_date] => 2008-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210681.pdf [firstpage_image] =>[orig_patent_app_number] => 12032647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032647
Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model Feb 15, 2008 Issued
Array ( [id] => 5478860 [patent_doc_number] => 20090201817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'METHOD OF OPTIMIZING A FLOW OF VALUE IN A NETWORK' [patent_app_type] => utility [patent_app_number] => 12/028408 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201817.pdf [firstpage_image] =>[orig_patent_app_number] => 12028408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/028408
METHOD OF OPTIMIZING A FLOW OF VALUE IN A NETWORK Feb 7, 2008 Abandoned
Array ( [id] => 7745295 [patent_doc_number] => 08108187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Method and system for surface analysis and envelope generation' [patent_app_type] => utility [patent_app_number] => 11/970757 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108187.pdf [firstpage_image] =>[orig_patent_app_number] => 11970757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970757
Method and system for surface analysis and envelope generation Jan 7, 2008 Issued
Array ( [id] => 7686835 [patent_doc_number] => 20090177456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'Mixed Decoupled Electromagnetic Circuit Solver' [patent_app_type] => utility [patent_app_number] => 11/968698 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5490 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177456.pdf [firstpage_image] =>[orig_patent_app_number] => 11968698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968698
Mixed Decoupled Electromagnetic Circuit Solver Jan 2, 2008 Abandoned
Array ( [id] => 5503506 [patent_doc_number] => 20090164194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Netlist Partitioning for Characterizing Effect of Within-Die Variations' [patent_app_type] => utility [patent_app_number] => 11/961787 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164194.pdf [firstpage_image] =>[orig_patent_app_number] => 11961787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961787
Netlist partitioning for characterizing effect of within-die variations Dec 19, 2007 Issued
Array ( [id] => 4894643 [patent_doc_number] => 20080103742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Coupled Algorithms on Quadrilateral Grids for Generalized Axi-Symmetric Viscoelastic Fluid Flows' [patent_app_type] => utility [patent_app_number] => 11/961851 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12569 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20080103742.pdf [firstpage_image] =>[orig_patent_app_number] => 11961851 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961851
Coupled algorithms on quadrilateral grids for generalized axi-symmetric viscoelastic fluid flows Dec 19, 2007 Issued
Array ( [id] => 5423677 [patent_doc_number] => 20090150133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'APPARATUS AND METHOD FOR SIMULATING ONE OR MORE OPERATIONAL CHARACTERISTICS OF AN ELECTRONICS RACK' [patent_app_type] => utility [patent_app_number] => 11/950735 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150133.pdf [firstpage_image] =>[orig_patent_app_number] => 11950735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950735
Apparatus and method for simulating one or more operational characteristics of an electronics rack Dec 4, 2007 Issued
Array ( [id] => 5576679 [patent_doc_number] => 20090144041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'System and method for simulating a semiconductor wafer prober and a class memory test handler' [patent_app_type] => utility [patent_app_number] => 11/998481 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4222 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144041.pdf [firstpage_image] =>[orig_patent_app_number] => 11998481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/998481
System and method for simulating a semiconductor wafer prober and a class memory test handler Nov 29, 2007 Issued
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