
Bernard E. Cothran
Examiner (ID: 2209, Phone: (571)270-5594 , Office: P/2128 )
| Most Active Art Unit | 2128 |
| Art Unit(s) | 2128, 2147, 2123, 2188 |
| Total Applications | 420 |
| Issued Applications | 169 |
| Pending Applications | 55 |
| Abandoned Applications | 202 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5541012
[patent_doc_number] => 20090222817
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[patent_issue_date] => 2009-09-03
[patent_title] => 'Navigation in Simulated Workflows'
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[patent_app_country] => US
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Array
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Array
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[patent_title] => 'Method and apparatus for profiling a hardware/software embedded system'
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Array
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[patent_title] => 'Method and Apparatus of Handling Instruction Rejects, Partial Rejects, Stalls and Branch Wrong in a Simulation Model'
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Array
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[patent_title] => 'METHOD OF OPTIMIZING A FLOW OF VALUE IN A NETWORK'
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Array
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Array
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Array
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[patent_title] => 'Netlist Partitioning for Characterizing Effect of Within-Die Variations'
[patent_app_type] => utility
[patent_app_number] => 11/961787
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/961787 | Netlist partitioning for characterizing effect of within-die variations | Dec 19, 2007 | Issued |
Array
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[patent_title] => 'Coupled Algorithms on Quadrilateral Grids for Generalized Axi-Symmetric Viscoelastic Fluid Flows'
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Array
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[patent_title] => 'APPARATUS AND METHOD FOR SIMULATING ONE OR MORE OPERATIONAL CHARACTERISTICS OF AN ELECTRONICS RACK'
[patent_app_type] => utility
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Array
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[patent_title] => 'System and method for simulating a semiconductor wafer prober and a class memory test handler'
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Array
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Array
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Array
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Array
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Array
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