Bernard E. Souw

Array ( [id] => 4153937 [patent_doc_number] => 06107200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/265399 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7246 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107200.pdf [firstpage_image] =>[orig_patent_app_number] => 265399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297806 [patent_doc_number] => 06236113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Iridium composite barrier structure and method for same' [patent_app_type] => 1 [patent_app_number] => 9/263970 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3964 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236113.pdf [firstpage_image] =>[orig_patent_app_number] => 263970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258482 [patent_doc_number] => 06258641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors' [patent_app_type] => 1 [patent_app_number] => 9/244878 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2980 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258641.pdf [firstpage_image] =>[orig_patent_app_number] => 244878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4182489 [patent_doc_number] => 06150241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for producing a transistor with self-aligned contacts and field insulation' [patent_app_type] => 1 [patent_app_number] => 9/147438 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150241.pdf [firstpage_image] =>[orig_patent_app_number] => 147438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4098071 [patent_doc_number] => 06048784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Transistor having an improved salicided gate and method of construction' [patent_app_type] => 1 [patent_app_number] => 9/212189 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048784.pdf [firstpage_image] =>[orig_patent_app_number] => 212189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4172870 [patent_doc_number] => 06083821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Integrated circuit having a void between adjacent conductive lines' [patent_app_type] => 1 [patent_app_number] => 9/182858 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3278 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083821.pdf [firstpage_image] =>[orig_patent_app_number] => 182858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4348402 [patent_doc_number] => 06214713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Two step cap nitride deposition for forming gate electrodes' [patent_app_type] => 1 [patent_app_number] => 9/175869 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214713.pdf [firstpage_image] =>[orig_patent_app_number] => 175869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187982 [patent_doc_number] => 06153455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer' [patent_app_type] => 1 [patent_app_number] => 9/170619 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4345 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153455.pdf [firstpage_image] =>[orig_patent_app_number] => 170619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152082 [patent_doc_number] => 06124172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of making a semiconductor device having source/drain structures with self-aligned heavily-doped and lightly-doped regions' [patent_app_type] => 1 [patent_app_number] => 9/163688 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4070 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124172.pdf [firstpage_image] =>[orig_patent_app_number] => 163688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4222417 [patent_doc_number] => 06010954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices' [patent_app_type] => 1 [patent_app_number] => 9/156359 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010954.pdf [firstpage_image] =>[orig_patent_app_number] => 156359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4130454 [patent_doc_number] => 06033982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Scaled interconnect anodization for high frequency applications' [patent_app_type] => 1 [patent_app_number] => 9/149208 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5024 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033982.pdf [firstpage_image] =>[orig_patent_app_number] => 149208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131101 [patent_doc_number] => 06146953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Fabrication method for mosfet device' [patent_app_type] => 1 [patent_app_number] => 9/148078 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1781 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146953.pdf [firstpage_image] =>[orig_patent_app_number] => 148078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419090 [patent_doc_number] => 06506648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure' [patent_app_type] => B1 [patent_app_number] => 09/145818 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2164 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506648.pdf [firstpage_image] =>[orig_patent_app_number] => 09145818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236199 [patent_doc_number] => 06143659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method for manufacturing aluminum metal interconnection layer by atomic layer deposition method' [patent_app_type] => 1 [patent_app_number] => 9/141768 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3256 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143659.pdf [firstpage_image] =>[orig_patent_app_number] => 141768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4205220 [patent_doc_number] => 06077775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Process for making a semiconductor device with barrier film formation using a metal halide and products thereof' [patent_app_type] => 1 [patent_app_number] => 9/137089 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077775.pdf [firstpage_image] =>[orig_patent_app_number] => 137089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405511 [patent_doc_number] => 06232191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for forming a spacer for semiconductor manufacture' [patent_app_type] => 1 [patent_app_number] => 9/133718 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3689 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232191.pdf [firstpage_image] =>[orig_patent_app_number] => 133718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139567 [patent_doc_number] => 06060383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method for making multilayered coaxial interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/131919 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4857 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060383.pdf [firstpage_image] =>[orig_patent_app_number] => 131919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197544 [patent_doc_number] => 06013553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Zirconium and/or hafnium oxynitride gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/115773 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 5298 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013553.pdf [firstpage_image] =>[orig_patent_app_number] => 115773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4181343 [patent_doc_number] => 06020243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Zirconium and/or hafnium silicon-oxynitride gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/115859 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 19 [patent_no_of_words] => 6630 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020243.pdf [firstpage_image] =>[orig_patent_app_number] => 115859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4136766 [patent_doc_number] => 06015752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Elevated salicide technology' [patent_app_type] => 1 [patent_app_number] => 9/106769 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3012 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015752.pdf [firstpage_image] =>[orig_patent_app_number] => 106769 [rel_patent_id] =>[rel_patent_doc_number] =>)