| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3911000
[patent_doc_number] => 06001709
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Modified LOCOS isolation process for semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/062638
[patent_app_country] => US
[patent_app_date] => 1998-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2089
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001709.pdf
[firstpage_image] =>[orig_patent_app_number] => 062638
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/062638 | Modified LOCOS isolation process for semiconductor devices | Apr 19, 1998 | Issued |
Array
(
[id] => 4084652
[patent_doc_number] => 06025235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Short channel transistor having resistive gate extensions'
[patent_app_type] => 1
[patent_app_number] => 9/037488
[patent_app_country] => US
[patent_app_date] => 1998-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 4311
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025235.pdf
[firstpage_image] =>[orig_patent_app_number] => 037488
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/037488 | Short channel transistor having resistive gate extensions | Mar 9, 1998 | Issued |
Array
(
[id] => 3944274
[patent_doc_number] => 05998269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Technology for high performance buried contact and tungsten polycide gate integration'
[patent_app_type] => 1
[patent_app_number] => 9/035139
[patent_app_country] => US
[patent_app_date] => 1998-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 2717
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/998/05998269.pdf
[firstpage_image] =>[orig_patent_app_number] => 035139
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/035139 | Technology for high performance buried contact and tungsten polycide gate integration | Mar 4, 1998 | Issued |
Array
(
[id] => 3910771
[patent_doc_number] => 06001695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method to form ultra-short channel MOSFET with a gate-side airgap structure'
[patent_app_type] => 1
[patent_app_number] => 9/033948
[patent_app_country] => US
[patent_app_date] => 1998-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2530
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 409
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001695.pdf
[firstpage_image] =>[orig_patent_app_number] => 033948
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/033948 | Method to form ultra-short channel MOSFET with a gate-side airgap structure | Mar 1, 1998 | Issued |
Array
(
[id] => 4236054
[patent_doc_number] => 06143649
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Method for making semiconductor devices having gradual slope contacts'
[patent_app_type] => 1
[patent_app_number] => 9/019009
[patent_app_country] => US
[patent_app_date] => 1998-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4919
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/143/06143649.pdf
[firstpage_image] =>[orig_patent_app_number] => 019009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/019009 | Method for making semiconductor devices having gradual slope contacts | Feb 4, 1998 | Issued |
Array
(
[id] => 3945628
[patent_doc_number] => 05953628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Method for forming wiring for a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/014129
[patent_app_country] => US
[patent_app_date] => 1998-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 22
[patent_no_of_words] => 2663
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/953/05953628.pdf
[firstpage_image] =>[orig_patent_app_number] => 014129
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/014129 | Method for forming wiring for a semiconductor device | Jan 26, 1998 | Issued |
Array
(
[id] => 4029418
[patent_doc_number] => 05994183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Method for forming charge storage structure'
[patent_app_type] => 1
[patent_app_number] => 8/996696
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2562
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994183.pdf
[firstpage_image] =>[orig_patent_app_number] => 996696
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996696 | Method for forming charge storage structure | Dec 22, 1997 | Issued |
| 08/967048 | METHOD OF FORMING LOW TEMPERATURE METAL FILL REGIONS FOR OHMIC CONTACTS AND FOR VIA OPENINGS BETWEEN SPACED APART METAL LAYERS AND SEMICONDUCTOR STRUCTURE FABRICATED THEREFROM | Nov 9, 1997 | Abandoned |
Array
(
[id] => 4222501
[patent_doc_number] => 06010960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Method and system for providing an interconnect having reduced failure rates due to voids'
[patent_app_type] => 1
[patent_app_number] => 8/959591
[patent_app_country] => US
[patent_app_date] => 1997-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 1723
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/010/06010960.pdf
[firstpage_image] =>[orig_patent_app_number] => 959591
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/959591 | Method and system for providing an interconnect having reduced failure rates due to voids | Oct 28, 1997 | Issued |
Array
(
[id] => 4153767
[patent_doc_number] => 06107190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/959268
[patent_app_country] => US
[patent_app_date] => 1997-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 26
[patent_no_of_words] => 7999
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/107/06107190.pdf
[firstpage_image] =>[orig_patent_app_number] => 959268
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/959268 | Method of fabricating semiconductor device | Oct 27, 1997 | Issued |
Array
(
[id] => 4247505
[patent_doc_number] => 06221760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Semiconductor device having a silicide structure'
[patent_app_type] => 1
[patent_app_number] => 8/954427
[patent_app_country] => US
[patent_app_date] => 1997-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 3283
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221760.pdf
[firstpage_image] =>[orig_patent_app_number] => 954427
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/954427 | Semiconductor device having a silicide structure | Oct 19, 1997 | Issued |
Array
(
[id] => 4087561
[patent_doc_number] => 06133139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof'
[patent_app_type] => 1
[patent_app_number] => 8/947244
[patent_app_country] => US
[patent_app_date] => 1997-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 7253
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/133/06133139.pdf
[firstpage_image] =>[orig_patent_app_number] => 947244
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947244 | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof | Oct 7, 1997 | Issued |
Array
(
[id] => 4246184
[patent_doc_number] => 06136677
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Method of fabricating semiconductor chips with silicide and implanted junctions'
[patent_app_type] => 1
[patent_app_number] => 8/937781
[patent_app_country] => US
[patent_app_date] => 1997-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2701
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/136/06136677.pdf
[firstpage_image] =>[orig_patent_app_number] => 937781
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937781 | Method of fabricating semiconductor chips with silicide and implanted junctions | Sep 24, 1997 | Issued |
Array
(
[id] => 4139039
[patent_doc_number] => 06060346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/931238
[patent_app_country] => US
[patent_app_date] => 1997-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3585
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060346.pdf
[firstpage_image] =>[orig_patent_app_number] => 931238
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/931238 | Semiconductor device and method for manufacturing the same | Sep 15, 1997 | Issued |
Array
(
[id] => 4197770
[patent_doc_number] => 06013569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'One step salicide process without bridging'
[patent_app_type] => 1
[patent_app_number] => 8/888752
[patent_app_country] => US
[patent_app_date] => 1997-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 5994
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/013/06013569.pdf
[firstpage_image] =>[orig_patent_app_number] => 888752
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/888752 | One step salicide process without bridging | Jul 6, 1997 | Issued |
| 08/873937 | USING AN ELEVATED SILICIDE AS A DIFFUSION SOURCE FOR DEEP SUB-MICRON AND BEYOND CMOS | Jun 11, 1997 | Abandoned |
Array
(
[id] => 4205206
[patent_doc_number] => 06077774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Method of forming ultra-thin and conformal diffusion barriers encapsulating copper'
[patent_app_type] => 1
[patent_app_number] => 8/820744
[patent_app_country] => US
[patent_app_date] => 1997-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 2713
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/077/06077774.pdf
[firstpage_image] =>[orig_patent_app_number] => 820744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/820744 | Method of forming ultra-thin and conformal diffusion barriers encapsulating copper | Mar 18, 1997 | Issued |
Array
(
[id] => 4215048
[patent_doc_number] => 06110824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Wire shape conferring reduced crosstalk and formation methods'
[patent_app_type] => 1
[patent_app_number] => 8/816586
[patent_app_country] => US
[patent_app_date] => 1997-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 2346
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110824.pdf
[firstpage_image] =>[orig_patent_app_number] => 816586
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/816586 | Wire shape conferring reduced crosstalk and formation methods | Mar 12, 1997 | Issued |
Array
(
[id] => 4125210
[patent_doc_number] => 06127249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Metal silicidation methods and methods for using same'
[patent_app_type] => 1
[patent_app_number] => 8/803528
[patent_app_country] => US
[patent_app_date] => 1997-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 36
[patent_no_of_words] => 8163
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/127/06127249.pdf
[firstpage_image] =>[orig_patent_app_number] => 803528
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/803528 | Metal silicidation methods and methods for using same | Feb 19, 1997 | Issued |
Array
(
[id] => 3994232
[patent_doc_number] => 05985754
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method of forming a void-free contact plug'
[patent_app_type] => 1
[patent_app_number] => 8/766028
[patent_app_country] => US
[patent_app_date] => 1996-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 4518
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/985/05985754.pdf
[firstpage_image] =>[orig_patent_app_number] => 766028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766028 | Method of forming a void-free contact plug | Dec 12, 1996 | Issued |