Search

Bernarr E. Gregory

Examiner (ID: 11710, Phone: (571)272-6972 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
2202, 3646, 3648, 3642, 2766, 3662
Total Applications
4661
Issued Applications
4105
Pending Applications
272
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1297363 [patent_doc_number] => 06627503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method of forming a multilayer dielectric stack' [patent_app_type] => B2 [patent_app_number] => 10/137567 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3890 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627503.pdf [firstpage_image] =>[orig_patent_app_number] => 10137567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137567
Method of forming a multilayer dielectric stack Apr 29, 2002 Issued
Array ( [id] => 7631374 [patent_doc_number] => 06635558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions' [patent_app_type] => B2 [patent_app_number] => 10/128933 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3378 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635558.pdf [firstpage_image] =>[orig_patent_app_number] => 10128933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/128933
Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions Apr 22, 2002 Issued
Array ( [id] => 6260527 [patent_doc_number] => 20020187592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method for forming a thin-film transistor' [patent_app_type] => new [patent_app_number] => 10/121537 [patent_app_country] => US [patent_app_date] => 2002-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2420 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187592.pdf [firstpage_image] =>[orig_patent_app_number] => 10121537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/121537
Method for forming a thin-film transistor Apr 10, 2002 Issued
Array ( [id] => 6863726 [patent_doc_number] => 20030189252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Physically deposited layer to electrically connect circuit edit connection targets' [patent_app_type] => new [patent_app_number] => 10/117617 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6848 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189252.pdf [firstpage_image] =>[orig_patent_app_number] => 10117617 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117617
Physically deposited layer to electrically connect circuit edit connection targets Apr 4, 2002 Issued
Array ( [id] => 5901002 [patent_doc_number] => 20020140029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Method for frabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/083187 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20020140029.pdf [firstpage_image] =>[orig_patent_app_number] => 10083187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083187
Method for fabricating semiconductor device Feb 25, 2002 Issued
Array ( [id] => 6237578 [patent_doc_number] => 20020043714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Premold type semiconductor package and process for manufacturing same' [patent_app_type] => new [patent_app_number] => 10/020222 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5172 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043714.pdf [firstpage_image] =>[orig_patent_app_number] => 10020222 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020222
Premold type semiconductor package Dec 17, 2001 Issued
Array ( [id] => 6577919 [patent_doc_number] => 20020041034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Interconnections for a semiconductor device and method for forming same' [patent_app_type] => new [patent_app_number] => 10/015337 [patent_app_country] => US [patent_app_date] => 2001-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2577 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041034.pdf [firstpage_image] =>[orig_patent_app_number] => 10015337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015337
Interconnections for a semiconductor device and method for forming same Dec 10, 2001 Issued
Array ( [id] => 6522727 [patent_doc_number] => 20020109206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Lateral PNP-type transistor based on a vertical NPN-structure and process for producing such PNP-type transistor' [patent_app_type] => new [patent_app_number] => 10/007917 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109206.pdf [firstpage_image] =>[orig_patent_app_number] => 10007917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007917
Lateral PNP-type transistor based on a vertical NPN-structure and process for producing such PNP-type transistor Dec 6, 2001 Abandoned
Array ( [id] => 1164936 [patent_doc_number] => 06756236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method of producing a ferroelectric memory and a memory device' [patent_app_type] => B2 [patent_app_number] => 10/006347 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9606 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756236.pdf [firstpage_image] =>[orig_patent_app_number] => 10006347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/006347
Method of producing a ferroelectric memory and a memory device Dec 3, 2001 Issued
Array ( [id] => 1210902 [patent_doc_number] => 06713831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Borderless contact architecture' [patent_app_type] => B1 [patent_app_number] => 10/010837 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 7020 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713831.pdf [firstpage_image] =>[orig_patent_app_number] => 10010837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010837
Borderless contact architecture Dec 3, 2001 Issued
Array ( [id] => 6405929 [patent_doc_number] => 20020037629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Chemical mechanical polishing for forming a shallow trench isolation structure' [patent_app_type] => new [patent_app_number] => 09/991395 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2225 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037629.pdf [firstpage_image] =>[orig_patent_app_number] => 09991395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991395
Chemical mechanical polishing for forming a shallow trench isolation structure Nov 19, 2001 Issued
Array ( [id] => 5917981 [patent_doc_number] => 20020113263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same' [patent_app_type] => new [patent_app_number] => 10/007081 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6036 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113263.pdf [firstpage_image] =>[orig_patent_app_number] => 10007081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007081
Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same Nov 12, 2001 Issued
Array ( [id] => 6081063 [patent_doc_number] => 20020081785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Process for producing an MOS field effect transistor with a recombination zone' [patent_app_type] => new [patent_app_number] => 10/008797 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2625 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081785.pdf [firstpage_image] =>[orig_patent_app_number] => 10008797 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008797
Process for producing an MOS field effect transistor with a recombination zone Nov 12, 2001 Issued
Array ( [id] => 6792178 [patent_doc_number] => 20030087522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method of forming reliable Cu interconnects' [patent_app_type] => new [patent_app_number] => 09/986267 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3410 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20030087522.pdf [firstpage_image] =>[orig_patent_app_number] => 09986267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986267
Method of forming reliable Cu interconnects Nov 7, 2001 Issued
Array ( [id] => 1390222 [patent_doc_number] => 06544859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing' [patent_app_type] => B2 [patent_app_number] => 10/003130 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4600 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544859.pdf [firstpage_image] =>[orig_patent_app_number] => 10003130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003130
Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing Oct 31, 2001 Issued
Array ( [id] => 6755946 [patent_doc_number] => 20030003723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/964527 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2942 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003723.pdf [firstpage_image] =>[orig_patent_app_number] => 09964527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964527
Method for manufacturing semiconductor device Sep 27, 2001 Abandoned
Array ( [id] => 6720937 [patent_doc_number] => 20030054626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF' [patent_app_type] => new [patent_app_number] => 09/952527 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3210 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054626.pdf [firstpage_image] =>[orig_patent_app_number] => 09952527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952527
Method of forming a bond pad and structure thereof Sep 13, 2001 Issued
Array ( [id] => 5798603 [patent_doc_number] => 20020008308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Open-cavity semiconductor die package' [patent_app_type] => new [patent_app_number] => 09/950702 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5592 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008308.pdf [firstpage_image] =>[orig_patent_app_number] => 09950702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950702
Open-cavity semiconductor die package Sep 12, 2001 Issued
Array ( [id] => 1318431 [patent_doc_number] => 06605524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Bumping process to increase bump height and to create a more robust bump structure' [patent_app_type] => B1 [patent_app_number] => 09/950227 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5281 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605524.pdf [firstpage_image] =>[orig_patent_app_number] => 09950227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950227
Bumping process to increase bump height and to create a more robust bump structure Sep 9, 2001 Issued
Array ( [id] => 6778815 [patent_doc_number] => 20030049896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'METHOD FOR MAKING AN ACTIVE PIXEL SENSOR' [patent_app_type] => new [patent_app_number] => 09/682477 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4527 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049896.pdf [firstpage_image] =>[orig_patent_app_number] => 09682477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/682477
Method for making an active pixel sensor Sep 6, 2001 Issued
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