Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17410005 [patent_doc_number] => 11250901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 17/103374 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103374
Protocol for memory power-mode control Nov 23, 2020 Issued
Array ( [id] => 17730562 [patent_doc_number] => 11386960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/103691 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 22167 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103691
Semiconductor memory device Nov 23, 2020 Issued
Array ( [id] => 17353018 [patent_doc_number] => 11227662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/103396 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 25335 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103396
Semiconductor memory Nov 23, 2020 Issued
Array ( [id] => 17438768 [patent_doc_number] => 11264108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor memory device for storing multivalued data [patent_app_type] => utility [patent_app_number] => 17/101553 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 92 [patent_no_of_words] => 28729 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101553
Semiconductor memory device for storing multivalued data Nov 22, 2020 Issued
Array ( [id] => 16752262 [patent_doc_number] => 20210104274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL [patent_app_type] => utility [patent_app_number] => 17/101431 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101431
Semiconductor memory device which stores plural data in a cell Nov 22, 2020 Issued
Array ( [id] => 17745890 [patent_doc_number] => 11393976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Carbon-based volatile and non-volatile memristors [patent_app_type] => utility [patent_app_number] => 17/094141 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 138 [patent_no_of_words] => 21617 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094141
Carbon-based volatile and non-volatile memristors Nov 9, 2020 Issued
Array ( [id] => 18974948 [patent_doc_number] => 20240055040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => A DYNAMIC RANDOM ACCESS MEMORY (DRAM) STRUCTURE WITH BODY BIAS VOLTAGE THAT CAN BE ADAPTED TO THE ACCESS PATTERN OF CELLS [patent_app_type] => utility [patent_app_number] => 17/766326 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17766326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/766326
Dynamic random access memory (DRAM) structure with body bias voltage that can be adapted to the access pattern of cells Nov 5, 2020 Issued
Array ( [id] => 17971118 [patent_doc_number] => 11488665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor memory having both volatile and non-volatile functionality and method of operating [patent_app_type] => utility [patent_app_number] => 17/087884 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 18601 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087884
Semiconductor memory having both volatile and non-volatile functionality and method of operating Nov 2, 2020 Issued
Array ( [id] => 17583078 [patent_doc_number] => 20220139933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MEMORY CELL AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/085444 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085444
Memory cell and methods thereof Oct 29, 2020 Issued
Array ( [id] => 16887450 [patent_doc_number] => 20210173647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => ORTHOGONAL DATA TRANSPOSITION SYSTEM AND METHOD DURING DATA TRANSFERS TO/FROM A PROCESSING ARRAY [patent_app_type] => utility [patent_app_number] => 17/082914 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082914
Orthogonal data transposition system and method during data transfers to/from a processing array Oct 27, 2020 Issued
Array ( [id] => 17424363 [patent_doc_number] => 11257825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-22 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/082856 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082856
Semiconductor device and manufacturing method thereof Oct 27, 2020 Issued
Array ( [id] => 16964747 [patent_doc_number] => 20210216246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/081869 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081869
RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS Oct 26, 2020 Abandoned
Array ( [id] => 17092687 [patent_doc_number] => 11120881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Charge pump for use in non-volatile flash memory devices [patent_app_type] => utility [patent_app_number] => 17/075691 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6609 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075691
Charge pump for use in non-volatile flash memory devices Oct 19, 2020 Issued
Array ( [id] => 17310276 [patent_doc_number] => 11211403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Nonvolatile memory device having a vertical structure and a memory system including the same [patent_app_type] => utility [patent_app_number] => 17/073653 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 13396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073653
Nonvolatile memory device having a vertical structure and a memory system including the same Oct 18, 2020 Issued
Array ( [id] => 17560766 [patent_doc_number] => 11317510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Load reduced memory module [patent_app_type] => utility [patent_app_number] => 17/072775 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14270 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072775
Load reduced memory module Oct 15, 2020 Issued
Array ( [id] => 17424079 [patent_doc_number] => 11257540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Write data processing methods associated with computational memory cells [patent_app_type] => utility [patent_app_number] => 17/067439 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067439
Write data processing methods associated with computational memory cells Oct 8, 2020 Issued
Array ( [id] => 17454789 [patent_doc_number] => 11269648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Apparatuses and methods for ordering bits in a memory device [patent_app_type] => utility [patent_app_number] => 17/065749 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065749
Apparatuses and methods for ordering bits in a memory device Oct 7, 2020 Issued
Array ( [id] => 17523148 [patent_doc_number] => 20220108997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => LOW-VOLTAGE FLASH MEMORY INTEGRATED WITH A VERTICAL FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/062647 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062647
Low-voltage flash memory integrated with a vertical field effect transistor Oct 4, 2020 Issued
Array ( [id] => 16752260 [patent_doc_number] => 20210104272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 17/023414 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023414
Semiconductor apparatus Sep 16, 2020 Issued
Array ( [id] => 16959165 [patent_doc_number] => 11063048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 17/022679 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 84 [patent_no_of_words] => 30001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022679
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor Sep 15, 2020 Issued
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