Search

Bernarr E. Gregory

Examiner (ID: 11710, Phone: (571)272-6972 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
2202, 3646, 3648, 3642, 2766, 3662
Total Applications
4661
Issued Applications
4105
Pending Applications
272
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6060324 [patent_doc_number] => 20020030229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Implementing contacts for bodies of semiconductor-on-insulator transistors' [patent_app_type] => new [patent_app_number] => 09/941221 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2521 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030229.pdf [firstpage_image] =>[orig_patent_app_number] => 09941221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941221
Implementing contacts for bodies of semiconductor-on-insulator transistors Aug 27, 2001 Abandoned
Array ( [id] => 6716058 [patent_doc_number] => 20030027406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Gettering of SOI wafers without regions of heavy doping' [patent_app_type] => new [patent_app_number] => 09/920577 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1535 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027406.pdf [firstpage_image] =>[orig_patent_app_number] => 09920577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920577
Gettering of SOI wafers without regions of heavy doping Jul 31, 2001 Abandoned
Array ( [id] => 6713817 [patent_doc_number] => 20030025165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'BURIED CHANNEL PMOS TRANSISTOR IN DUAL GATE CMOS WITH REDUCED MASKING STEPS' [patent_app_type] => new [patent_app_number] => 09/920157 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2645 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025165.pdf [firstpage_image] =>[orig_patent_app_number] => 09920157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920157
Buried channel PMOS transistor in dual gate CMOS with reduced masking steps Jul 31, 2001 Issued
Array ( [id] => 6742941 [patent_doc_number] => 20030020124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Stabilization for thin substrates' [patent_app_type] => new [patent_app_number] => 09/915807 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1250 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020124.pdf [firstpage_image] =>[orig_patent_app_number] => 09915807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915807
Stabilization for thin substrates Jul 25, 2001 Issued
Array ( [id] => 1402647 [patent_doc_number] => 06534420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Methods for forming dielectric materials and methods for forming semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 09/908767 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5167 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534420.pdf [firstpage_image] =>[orig_patent_app_number] => 09908767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908767
Methods for forming dielectric materials and methods for forming semiconductor devices Jul 17, 2001 Issued
Array ( [id] => 5870584 [patent_doc_number] => 20020047148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Methods of manufacturing integrated circuit capacitors having ruthenium upper electrodes and capacitors formed thereby' [patent_app_type] => new [patent_app_number] => 09/899867 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4727 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047148.pdf [firstpage_image] =>[orig_patent_app_number] => 09899867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899867
Methods of manufacturing integrated circuit capacitors having ruthenium upper electrodes and capacitors formed thereby Jul 4, 2001 Abandoned
Array ( [id] => 6901534 [patent_doc_number] => 20010023117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Methods of treating surfaces of substrates' [patent_app_type] => new [patent_app_number] => 09/863506 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5590 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023117.pdf [firstpage_image] =>[orig_patent_app_number] => 09863506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863506
Methods of treating surfaces of substrates May 21, 2001 Issued
Array ( [id] => 1397381 [patent_doc_number] => 06531401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method of cleaning a substrate surface using a frozen material' [patent_app_type] => B2 [patent_app_number] => 09/863507 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5556 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531401.pdf [firstpage_image] =>[orig_patent_app_number] => 09863507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863507
Method of cleaning a substrate surface using a frozen material May 21, 2001 Issued
Array ( [id] => 6896208 [patent_doc_number] => 20010026998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Methods of treating surfaces of substrates' [patent_app_type] => new [patent_app_number] => 09/863607 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5589 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026998.pdf [firstpage_image] =>[orig_patent_app_number] => 09863607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863607
Methods of treating surfaces of substrates May 21, 2001 Issued
Array ( [id] => 1408918 [patent_doc_number] => 06528350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method for fabricating a metal plated spring structure' [patent_app_type] => B2 [patent_app_number] => 09/863237 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 4508 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528350.pdf [firstpage_image] =>[orig_patent_app_number] => 09863237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863237
Method for fabricating a metal plated spring structure May 20, 2001 Issued
Array ( [id] => 1379703 [patent_doc_number] => 06555482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor' [patent_app_type] => B2 [patent_app_number] => 09/812717 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555482.pdf [firstpage_image] =>[orig_patent_app_number] => 09812717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812717
Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor Mar 19, 2001 Issued
Array ( [id] => 1500316 [patent_doc_number] => 06486033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'SAC method for embedded DRAM devices' [patent_app_type] => B1 [patent_app_number] => 09/808927 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2682 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486033.pdf [firstpage_image] =>[orig_patent_app_number] => 09808927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808927
SAC method for embedded DRAM devices Mar 15, 2001 Issued
Array ( [id] => 5844532 [patent_doc_number] => 20020132413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method of fabricating a MOS transistor' [patent_app_type] => new [patent_app_number] => 09/803887 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2284 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132413.pdf [firstpage_image] =>[orig_patent_app_number] => 09803887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803887
Method of fabricating a MOS transistor Mar 12, 2001 Abandoned
Array ( [id] => 6529978 [patent_doc_number] => 20020192884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Method for forming thin film transistor with reduced metal impurities' [patent_app_type] => new [patent_app_number] => 09/799047 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1831 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192884.pdf [firstpage_image] =>[orig_patent_app_number] => 09799047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799047
Method for forming thin film transistor with reduced metal impurities Mar 5, 2001 Abandoned
Array ( [id] => 5873983 [patent_doc_number] => 20020048827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor-package measuring method, measuring socket, and semiconductor package' [patent_app_type] => new [patent_app_number] => 09/793607 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2888 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048827.pdf [firstpage_image] =>[orig_patent_app_number] => 09793607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793607
Semiconductor-package measuring method, measuring socket, and semiconductor package Feb 26, 2001 Issued
Array ( [id] => 1467013 [patent_doc_number] => 06458671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of providing a shallow trench in a deep-trench device' [patent_app_type] => B1 [patent_app_number] => 09/784997 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3692 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458671.pdf [firstpage_image] =>[orig_patent_app_number] => 09784997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784997
Method of providing a shallow trench in a deep-trench device Feb 15, 2001 Issued
Array ( [id] => 6891243 [patent_doc_number] => 20010017405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Solid-state image pickup device and a method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/781217 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5669 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017405.pdf [firstpage_image] =>[orig_patent_app_number] => 09781217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781217
Solid-state image pickup device and a method of manufacturing the same Feb 12, 2001 Issued
Array ( [id] => 1366283 [patent_doc_number] => 06566147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method for controlling deposition of dielectric films' [patent_app_type] => B2 [patent_app_number] => 09/776217 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9206 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566147.pdf [firstpage_image] =>[orig_patent_app_number] => 09776217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776217
Method for controlling deposition of dielectric films Feb 1, 2001 Issued
Array ( [id] => 1361072 [patent_doc_number] => 06569692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Automated method of controlling photoresist develop time to control critical dimensions, and system for accomplishing same' [patent_app_type] => B1 [patent_app_number] => 09/776087 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569692.pdf [firstpage_image] =>[orig_patent_app_number] => 09776087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776087
Automated method of controlling photoresist develop time to control critical dimensions, and system for accomplishing same Feb 1, 2001 Issued
Array ( [id] => 1509329 [patent_doc_number] => 06441435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'SOI device with wrap-around contact to underside of body, and method of making' [patent_app_type] => B1 [patent_app_number] => 09/773037 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441435.pdf [firstpage_image] =>[orig_patent_app_number] => 09773037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773037
SOI device with wrap-around contact to underside of body, and method of making Jan 30, 2001 Issued
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