Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15351097 [patent_doc_number] => 20200013440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => DELAY CIRCUIT AND SEMICONDUCTOR SYSTEM USING THE DELAY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/200304 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200304
Delay circuit and semiconductor system using the delay circuit Nov 25, 2018 Issued
Array ( [id] => 16308474 [patent_doc_number] => 10777279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Non-volatile memory device and method of erasing the same [patent_app_type] => utility [patent_app_number] => 16/197886 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197886
Non-volatile memory device and method of erasing the same Nov 20, 2018 Issued
Array ( [id] => 15369209 [patent_doc_number] => 20200020369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/198264 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198264
Semiconductor devices Nov 20, 2018 Issued
Array ( [id] => 15029841 [patent_doc_number] => 20190325925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/198460 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198460
Semiconductor device Nov 20, 2018 Issued
Array ( [id] => 16279928 [patent_doc_number] => 10762966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Memory arrays and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/174318 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174318
Memory arrays and methods of forming the same Oct 29, 2018 Issued
Array ( [id] => 16417634 [patent_doc_number] => 10825534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Per row activation count values embedded in storage cell array storage cells [patent_app_type] => utility [patent_app_number] => 16/172460 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172460
Per row activation count values embedded in storage cell array storage cells Oct 25, 2018 Issued
Array ( [id] => 15921595 [patent_doc_number] => 10658044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Semiconductor memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/170854 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 12079 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170854
Semiconductor memory device and operating method thereof Oct 24, 2018 Issued
Array ( [id] => 16172609 [patent_doc_number] => 10714185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Event counters for memory operations [patent_app_type] => utility [patent_app_number] => 16/168952 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6612 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168952
Event counters for memory operations Oct 23, 2018 Issued
Array ( [id] => 16147673 [patent_doc_number] => 10706911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Sense amplifier for sensing multi-level cell and memory device including the sense amplifier [patent_app_type] => utility [patent_app_number] => 16/156052 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 58 [patent_no_of_words] => 18032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156052 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156052
Sense amplifier for sensing multi-level cell and memory device including the sense amplifier Oct 9, 2018 Issued
Array ( [id] => 16471775 [patent_doc_number] => 20200373313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC APPARATUS, AND METHOD OF READING DATA [patent_app_type] => utility [patent_app_number] => 16/767643 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16767643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/767643
Semiconductor memory device, electronic apparatus, and method of reading data Oct 9, 2018 Issued
Array ( [id] => 14187391 [patent_doc_number] => 20190113400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => MICROFABRICATED MAGNETOSTRICTIVE RESONATOR [patent_app_type] => utility [patent_app_number] => 16/156555 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156555
Microfabricated magnetostrictive resonator Oct 9, 2018 Issued
Array ( [id] => 15640823 [patent_doc_number] => 10593414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method of propagating magnetic domain wall in magnetic devices [patent_app_type] => utility [patent_app_number] => 16/155158 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 10002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155158
Method of propagating magnetic domain wall in magnetic devices Oct 8, 2018 Issued
Array ( [id] => 14627511 [patent_doc_number] => 20190227123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SEMICONDUCTOR STORAGE DEVICE, OPERATING METHOD THEREOF AND ANALYSIS SYSTEM [patent_app_type] => utility [patent_app_number] => 16/153844 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153844
Semiconductor storage device, operating method thereof and analysis system Oct 7, 2018 Issued
Array ( [id] => 16201757 [patent_doc_number] => 10726932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Storage device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/154334 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 15822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154334
Storage device and method of operating the same Oct 7, 2018 Issued
Array ( [id] => 15984231 [patent_doc_number] => 10672450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 16/139636 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139636
Protocol for memory power-mode control Sep 23, 2018 Issued
Array ( [id] => 15984231 [patent_doc_number] => 10672450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 16/139636 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139636
Protocol for memory power-mode control Sep 23, 2018 Issued
Array ( [id] => 15984231 [patent_doc_number] => 10672450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 16/139636 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139636
Protocol for memory power-mode control Sep 23, 2018 Issued
Array ( [id] => 15984231 [patent_doc_number] => 10672450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 16/139636 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139636
Protocol for memory power-mode control Sep 23, 2018 Issued
Array ( [id] => 16201728 [patent_doc_number] => 10726903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Row-determining circuit, DRAM, and method for refreshing a memory array [patent_app_type] => utility [patent_app_number] => 16/138020 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5510 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138020 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138020
Row-determining circuit, DRAM, and method for refreshing a memory array Sep 20, 2018 Issued
Array ( [id] => 15167975 [patent_doc_number] => 10489483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-26 [patent_title] => Circuit arrangement and technique for setting matrix values in three-terminal memory cells [patent_app_type] => utility [patent_app_number] => 16/137758 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137758
Circuit arrangement and technique for setting matrix values in three-terminal memory cells Sep 20, 2018 Issued
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