
Bernarr E. Gregory
Examiner (ID: 16577)
| Most Active Art Unit | 3648 |
| Art Unit(s) | 3642, 3646, 2202, 3662, 3648, 2766 |
| Total Applications | 4684 |
| Issued Applications | 4115 |
| Pending Applications | 277 |
| Abandoned Applications | 314 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15518943
[patent_doc_number] => 10566065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Memory control device and memory control method
[patent_app_type] => utility
[patent_app_number] => 16/136492
[patent_app_country] => US
[patent_app_date] => 2018-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2507
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136492
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/136492 | Memory control device and memory control method | Sep 19, 2018 | Issued |
Array
(
[id] => 14110909
[patent_doc_number] => 20190097130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => PROTEIN-BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/136570
[patent_app_country] => US
[patent_app_date] => 2018-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6795
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136570
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/136570 | Protein-based nonvolatile memory device and method for manufacturing the same | Sep 19, 2018 | Issued |
Array
(
[id] => 15686391
[patent_doc_number] => 20200097859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => QUANTUM ALGORITHM CONCATENATION
[patent_app_type] => utility
[patent_app_number] => 16/137215
[patent_app_country] => US
[patent_app_date] => 2018-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12436
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137215
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/137215 | Quantum algorithm concatenation | Sep 19, 2018 | Issued |
Array
(
[id] => 13829179
[patent_doc_number] => 20190018074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-17
[patent_title] => ELECTRONIC CIRCUIT FOR COMPENSATING A SENSITIVITY DRIFT OF A HALL EFFECT ELEMENT DUE TO STRESS
[patent_app_type] => utility
[patent_app_number] => 16/132653
[patent_app_country] => US
[patent_app_date] => 2018-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10208
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132653
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/132653 | Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress | Sep 16, 2018 | Issued |
Array
(
[id] => 14858767
[patent_doc_number] => 10418117
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-17
[patent_title] => Semiconductor memory device for storing multivalued data
[patent_app_type] => utility
[patent_app_number] => 16/132208
[patent_app_country] => US
[patent_app_date] => 2018-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 92
[patent_no_of_words] => 28655
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132208
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/132208 | Semiconductor memory device for storing multivalued data | Sep 13, 2018 | Issued |
Array
(
[id] => 14919941
[patent_doc_number] => 10431297
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-01
[patent_title] => Semiconductor memory device which stores plural data in a cell
[patent_app_type] => utility
[patent_app_number] => 16/125601
[patent_app_country] => US
[patent_app_date] => 2018-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 61
[patent_figures_cnt] => 105
[patent_no_of_words] => 38488
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125601
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/125601 | Semiconductor memory device which stores plural data in a cell | Sep 6, 2018 | Issued |
Array
(
[id] => 15184339
[patent_doc_number] => 20190362761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/116818
[patent_app_country] => US
[patent_app_date] => 2018-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11452
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116818
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/116818 | Semiconductor storage device and memory system | Aug 28, 2018 | Issued |
Array
(
[id] => 15580211
[patent_doc_number] => 10580497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-03
[patent_title] => Memory device, memory system including the same, and method of operating the memory system
[patent_app_type] => utility
[patent_app_number] => 16/114644
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 8898
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114644
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114644 | Memory device, memory system including the same, and method of operating the memory system | Aug 27, 2018 | Issued |
Array
(
[id] => 18000992
[patent_doc_number] => 11502103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-15
[patent_title] => Memory cell with a ferroelectric capacitor integrated with a transtor gate
[patent_app_type] => utility
[patent_app_number] => 16/114272
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 21050
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114272
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114272 | Memory cell with a ferroelectric capacitor integrated with a transtor gate | Aug 27, 2018 | Issued |
Array
(
[id] => 14888677
[patent_doc_number] => 10424385
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-09-24
[patent_title] => Self-configuring integrated circuit device
[patent_app_type] => utility
[patent_app_number] => 16/114364
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6372
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114364
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114364 | Self-configuring integrated circuit device | Aug 27, 2018 | Issued |
Array
(
[id] => 14903721
[patent_doc_number] => 20190295626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/114178
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10729
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114178
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114178 | Semiconductor memory device | Aug 26, 2018 | Issued |
Array
(
[id] => 14888675
[patent_doc_number] => 10424384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-24
[patent_title] => Semiconductor memory device and control method of semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 16/114182
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 9178
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114182
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114182 | Semiconductor memory device and control method of semiconductor memory device | Aug 26, 2018 | Issued |
Array
(
[id] => 13799041
[patent_doc_number] => 20190013059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-10
[patent_title] => APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 16/112471
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12741
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112471
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112471 | Apparatuses and methods for controlling refresh operations | Aug 23, 2018 | Issued |
Array
(
[id] => 16293280
[patent_doc_number] => 10770133
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-08
[patent_title] => Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
[patent_app_type] => utility
[patent_app_number] => 16/111182
[patent_app_country] => US
[patent_app_date] => 2018-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8228
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111182
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/111182 | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits | Aug 22, 2018 | Issued |
Array
(
[id] => 13785657
[patent_doc_number] => 20190006367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
[patent_app_type] => utility
[patent_app_number] => 16/105730
[patent_app_country] => US
[patent_app_date] => 2018-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105730
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/105730 | Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor | Aug 19, 2018 | Issued |
Array
(
[id] => 14397333
[patent_doc_number] => 10311955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Resistive memory transition monitoring
[patent_app_type] => utility
[patent_app_number] => 16/058552
[patent_app_country] => US
[patent_app_date] => 2018-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4276
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16058552
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/058552 | Resistive memory transition monitoring | Aug 7, 2018 | Issued |
Array
(
[id] => 16803931
[patent_doc_number] => 10998893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Semiconductor device, delay circuit, and related method
[patent_app_type] => utility
[patent_app_number] => 16/085870
[patent_app_country] => US
[patent_app_date] => 2018-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 6544
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16085870
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/085870 | Semiconductor device, delay circuit, and related method | Jul 31, 2018 | Issued |
Array
(
[id] => 15732869
[patent_doc_number] => 10614867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-07
[patent_title] => Patterning of high density small feature size pillar structures
[patent_app_type] => utility
[patent_app_number] => 16/051272
[patent_app_country] => US
[patent_app_date] => 2018-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 6413
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051272
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/051272 | Patterning of high density small feature size pillar structures | Jul 30, 2018 | Issued |
Array
(
[id] => 14752545
[patent_doc_number] => 20190259446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => WRITE LEVEL ARBITER CIRCUITRY
[patent_app_type] => utility
[patent_app_number] => 16/051210
[patent_app_country] => US
[patent_app_date] => 2018-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5804
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051210
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/051210 | Write level arbiter circuitry | Jul 30, 2018 | Issued |
Array
(
[id] => 14752519
[patent_doc_number] => 20190259433
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => GAP DETECTION FOR CONSECUTIVE WRITE OPERATIONS OF A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/051202
[patent_app_country] => US
[patent_app_date] => 2018-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11952
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051202
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/051202 | Gap detection for consecutive write operations of a memory device | Jul 30, 2018 | Issued |