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Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14093617 [patent_doc_number] => 10242721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Shifting data in sensing circuitry [patent_app_type] => utility [patent_app_number] => 16/025236 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/025236
Shifting data in sensing circuitry Jul 1, 2018 Issued
Array ( [id] => 13514013 [patent_doc_number] => 20180308549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/022568 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022568
Semiconductor storage device Jun 27, 2018 Issued
Array ( [id] => 18520825 [patent_doc_number] => 11710720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Integrated multi-die partitioned voltage regulator [patent_app_type] => utility [patent_app_number] => 16/022515 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022515
Integrated multi-die partitioned voltage regulator Jun 27, 2018 Issued
Array ( [id] => 14825463 [patent_doc_number] => 10409741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Semiconductor memory apparatus and data input/output method thereof [patent_app_type] => utility [patent_app_number] => 16/020466 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7387 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020466
Semiconductor memory apparatus and data input/output method thereof Jun 26, 2018 Issued
Array ( [id] => 16034587 [patent_doc_number] => 10679720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Memory circuit and testing method thereof [patent_app_type] => utility [patent_app_number] => 16/015220 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11279 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015220
Memory circuit and testing method thereof Jun 21, 2018 Issued
Array ( [id] => 15518931 [patent_doc_number] => 10566059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Three dimensional NAND memory device with drain select gate electrode shared between multiple strings [patent_app_type] => utility [patent_app_number] => 16/014028 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 22774 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014028
Three dimensional NAND memory device with drain select gate electrode shared between multiple strings Jun 20, 2018 Issued
Array ( [id] => 14024143 [patent_doc_number] => 20190074065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => Methods of Operating Memory Devices Based on Sub-Block Positions and Related Memory Systems [patent_app_type] => utility [patent_app_number] => 16/004770 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004770
Methods of operating memory devices based on sub-block positions and related memory systems Jun 10, 2018 Issued
Array ( [id] => 15259661 [patent_doc_number] => 20190378564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/005662 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/005662
MEMORY DEVICE AND OPERATING METHOD THEREOF Jun 10, 2018 Abandoned
Array ( [id] => 15199827 [patent_doc_number] => 10497414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Circuitry for tracking bias voltage behavior [patent_app_type] => utility [patent_app_number] => 16/003996 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003996 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003996
Circuitry for tracking bias voltage behavior Jun 7, 2018 Issued
Array ( [id] => 15401217 [patent_doc_number] => 10541270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device [patent_app_type] => utility [patent_app_number] => 16/004195 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004195 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004195
Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device Jun 7, 2018 Issued
Array ( [id] => 13593485 [patent_doc_number] => 20180348291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHOD AND SYSTEM FOR DATA COLLECTION AND ANALYSIS FOR SEMICONDUCTOR MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/000707 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000707 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000707
Method and system for data collection and analysis for semiconductor manufacturing Jun 4, 2018 Issued
Array ( [id] => 13972601 [patent_doc_number] => 10215648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Electrodeposition processes for magnetostrictive resonators [patent_app_type] => utility [patent_app_number] => 15/996147 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 24769 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/996147
Electrodeposition processes for magnetostrictive resonators May 31, 2018 Issued
Array ( [id] => 14919871 [patent_doc_number] => 10431262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device [patent_app_type] => utility [patent_app_number] => 15/992160 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8844 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/992160
Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device May 28, 2018 Issued
Array ( [id] => 15316045 [patent_doc_number] => 10522740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Techniques for MRAM MTJ top electrode to metal layer interface including spacer [patent_app_type] => utility [patent_app_number] => 15/991004 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991004
Techniques for MRAM MTJ top electrode to metal layer interface including spacer May 28, 2018 Issued
Array ( [id] => 14800739 [patent_doc_number] => 10403378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Performing an operation on a memory cell of a memory system at a frequency based on temperature [patent_app_type] => utility [patent_app_number] => 15/991822 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6657 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991822
Performing an operation on a memory cell of a memory system at a frequency based on temperature May 28, 2018 Issued
Array ( [id] => 15854593 [patent_doc_number] => 10642579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/989382 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6395 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989382
Non-volatile memory May 24, 2018 Issued
Array ( [id] => 13499309 [patent_doc_number] => 20180301197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/987810 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987810
Semiconductor memory device May 22, 2018 Issued
Array ( [id] => 14151159 [patent_doc_number] => 10255963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Apparatus having dice to perform refresh operations [patent_app_type] => utility [patent_app_number] => 15/979057 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3959 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979057
Apparatus having dice to perform refresh operations May 13, 2018 Issued
Array ( [id] => 15687523 [patent_doc_number] => 20200098425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MEMORY APPARATUS AND METHOD OF CONTROLLING MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/612458 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16612458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/612458
Memory apparatus and method of controlling memory apparatus May 10, 2018 Issued
Array ( [id] => 15014763 [patent_doc_number] => 10453537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-22 [patent_title] => Techniques for reducing read voltage threshold calibration in non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/976536 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976536
Techniques for reducing read voltage threshold calibration in non-volatile memory May 9, 2018 Issued
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