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Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14800671 [patent_doc_number] => 10403343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Systems and methods utilizing serial configurations of magnetic memory devices [patent_app_type] => utility [patent_app_number] => 15/859250 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 14544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859250
Systems and methods utilizing serial configurations of magnetic memory devices Dec 28, 2017 Issued
Array ( [id] => 14177395 [patent_doc_number] => 10262718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => DRAM having a plurality of registers [patent_app_type] => utility [patent_app_number] => 15/855535 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855535
DRAM having a plurality of registers Dec 26, 2017 Issued
Array ( [id] => 13832129 [patent_doc_number] => 20190019549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/851792 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851792
Activation of memory core circuits in an integrated circuit Dec 21, 2017 Issued
Array ( [id] => 13187665 [patent_doc_number] => 10109358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Semiconductor memory device for storing multivalued data [patent_app_type] => utility [patent_app_number] => 15/845310 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 92 [patent_no_of_words] => 28638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845310
Semiconductor memory device for storing multivalued data Dec 17, 2017 Issued
Array ( [id] => 16911482 [patent_doc_number] => 11043532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/477262 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 10330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/477262
Semiconductor device Dec 12, 2017 Issued
Array ( [id] => 14737897 [patent_doc_number] => 10388357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Activation of memory core circuits in an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/831436 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4143 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831436
Activation of memory core circuits in an integrated circuit Dec 4, 2017 Issued
Array ( [id] => 13159249 [patent_doc_number] => 10096358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Semiconductor memory device which stores plural data in a cell [patent_app_type] => utility [patent_app_number] => 15/832557 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 103 [patent_no_of_words] => 38201 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832557
Semiconductor memory device which stores plural data in a cell Dec 4, 2017 Issued
Array ( [id] => 12744028 [patent_doc_number] => 20180139843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => LOAD REDUCED MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 15/814180 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814180
Load reduced memory module Nov 14, 2017 Issued
Array ( [id] => 14281589 [patent_doc_number] => 20190138079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => GROUPING CENTRAL PROCESSING UNIT MEMORIES BASED ON DYNAMIC CLOCK AND VOLTAGE SCALING TIMING TO IMPROVE DYNAMIC/LEAKAGE POWER USING ARRAY POWER MULTIPLEXERS [patent_app_type] => utility [patent_app_number] => 15/808538 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808538
Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexers Nov 8, 2017 Issued
Array ( [id] => 14284645 [patent_doc_number] => 20190139607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => FLOATING GATE OTP/MTP STRUCTURE AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 15/807160 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807160
Floating gate OTP/MTP structure and method for producing the same Nov 7, 2017 Issued
Array ( [id] => 14063491 [patent_doc_number] => 10236046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Method of propagating magnetic domain wall in magnetic devices [patent_app_type] => utility [patent_app_number] => 15/807464 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 7496 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807464
Method of propagating magnetic domain wall in magnetic devices Nov 7, 2017 Issued
Array ( [id] => 14525493 [patent_doc_number] => 10340017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Erase-verify method for three-dimensional memories and memory system [patent_app_type] => utility [patent_app_number] => 15/803986 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8195 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803986 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803986
Erase-verify method for three-dimensional memories and memory system Nov 5, 2017 Issued
Array ( [id] => 12375099 [patent_doc_number] => 09959925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/799073 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6855 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799073
Semiconductor device Oct 30, 2017 Issued
Array ( [id] => 13214345 [patent_doc_number] => 10121547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/798181 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 9170 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798181
Semiconductor memory device Oct 29, 2017 Issued
Array ( [id] => 12188507 [patent_doc_number] => 20180047443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 15/797135 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15422 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797135
Semiconductor integrated circuit device Oct 29, 2017 Issued
Array ( [id] => 13613059 [patent_doc_number] => 20180358079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/794628 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794628
Semiconductor device Oct 25, 2017 Issued
Array ( [id] => 13755481 [patent_doc_number] => 10170696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-01 [patent_title] => MnN and Heusler layers in magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 15/795096 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3404 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795096
MnN and Heusler layers in magnetic tunnel junctions Oct 25, 2017 Issued
Array ( [id] => 14429205 [patent_doc_number] => 10319416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Memory device including page buffers [patent_app_type] => utility [patent_app_number] => 15/792992 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792992
Memory device including page buffers Oct 24, 2017 Issued
Array ( [id] => 14220725 [patent_doc_number] => 20190122747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/790046 [patent_app_country] => US [patent_app_date] => 2017-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790046
Memory device and operating method thereof Oct 21, 2017 Issued
Array ( [id] => 12188796 [patent_doc_number] => 20180047731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor' [patent_app_type] => utility [patent_app_number] => 15/730525 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 31626 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730525
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor Oct 10, 2017 Issued
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