Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11925385 [patent_doc_number] => 09792969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Semiconductor device and semiconductor system' [patent_app_type] => utility [patent_app_number] => 15/432214 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432214
Semiconductor device and semiconductor system Feb 13, 2017 Issued
Array ( [id] => 12952975 [patent_doc_number] => 09837131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Semiconductor device and output circuit thereof [patent_app_type] => utility [patent_app_number] => 15/431778 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4971 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431778
Semiconductor device and output circuit thereof Feb 13, 2017 Issued
Array ( [id] => 12214656 [patent_doc_number] => 09911471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-06 [patent_title] => 'Input buffer circuit' [patent_app_type] => utility [patent_app_number] => 15/432864 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6520 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432864
Input buffer circuit Feb 13, 2017 Issued
Array ( [id] => 11665945 [patent_doc_number] => 20170154663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'APPARATUS HAVING DICE TO PERORM REFRESH OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/431383 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431383
Apparatus having dice to perorm refresh operations Feb 12, 2017 Issued
Array ( [id] => 12354651 [patent_doc_number] => 09953727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing [patent_app_type] => utility [patent_app_number] => 15/430170 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5442 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430170
Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing Feb 9, 2017 Issued
Array ( [id] => 13808157 [patent_doc_number] => 10181347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Semiconductor device, adjustment method thereof and data processing system [patent_app_type] => utility [patent_app_number] => 15/425402 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 17262 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425402
Semiconductor device, adjustment method thereof and data processing system Feb 5, 2017 Issued
Array ( [id] => 12214671 [patent_doc_number] => 09911486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Synchronous random access memory (SRAM) chip and two port SRAM array' [patent_app_type] => utility [patent_app_number] => 15/425242 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 12374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425242
Synchronous random access memory (SRAM) chip and two port SRAM array Feb 5, 2017 Issued
Array ( [id] => 12456600 [patent_doc_number] => 09984736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Magnetic storage device and memory system [patent_app_type] => utility [patent_app_number] => 15/426032 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 42 [patent_no_of_words] => 29534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426032
Magnetic storage device and memory system Feb 5, 2017 Issued
Array ( [id] => 12249914 [patent_doc_number] => 09922696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Circuits and micro-architecture for a DRAM-based processing unit' [patent_app_type] => utility [patent_app_number] => 15/425996 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425996
Circuits and micro-architecture for a DRAM-based processing unit Feb 5, 2017 Issued
Array ( [id] => 11830512 [patent_doc_number] => 09727254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Memory devices, systems and methods employing command/address calibration' [patent_app_type] => utility [patent_app_number] => 15/420350 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 25498 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420350 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420350
Memory devices, systems and methods employing command/address calibration Jan 30, 2017 Issued
Array ( [id] => 13629231 [patent_doc_number] => 20180366168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/061076 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16061076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/061076
Memory controller Jan 23, 2017 Issued
Array ( [id] => 11623195 [patent_doc_number] => 20170133382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor' [patent_app_type] => utility [patent_app_number] => 15/414009 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 31623 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414009
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor Jan 23, 2017 Issued
Array ( [id] => 11622906 [patent_doc_number] => 20170133093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/405945 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7547 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405945
Semiconductor memory device and operating method thereof Jan 12, 2017 Issued
Array ( [id] => 14124091 [patent_doc_number] => 10248906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Neuromorphic circuits for storing and generating connectivity information [patent_app_type] => utility [patent_app_number] => 15/392407 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/392407
Neuromorphic circuits for storing and generating connectivity information Dec 27, 2016 Issued
Array ( [id] => 12354537 [patent_doc_number] => 09953689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Memory device, related method, and related electronic device [patent_app_type] => utility [patent_app_number] => 15/393023 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6681 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393023
Memory device, related method, and related electronic device Dec 27, 2016 Issued
Array ( [id] => 12101896 [patent_doc_number] => 09858995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method for operating a memory device' [patent_app_type] => utility [patent_app_number] => 15/387792 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2779 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387792
Method for operating a memory device Dec 21, 2016 Issued
Array ( [id] => 12953002 [patent_doc_number] => 09837140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/389192 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6827 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389192
Semiconductor device Dec 21, 2016 Issued
Array ( [id] => 12515547 [patent_doc_number] => 10002650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-19 [patent_title] => Signal quality detection circuit for generating signal quality detection result according to two-dimensional nominal sampling point pattern and associated signal quality detection method [patent_app_type] => utility [patent_app_number] => 15/387602 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6157 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387602
Signal quality detection circuit for generating signal quality detection result according to two-dimensional nominal sampling point pattern and associated signal quality detection method Dec 20, 2016 Issued
Array ( [id] => 11557569 [patent_doc_number] => 20170103814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/382862 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9422 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382862
Semiconductor memory device Dec 18, 2016 Issued
Array ( [id] => 12095610 [patent_doc_number] => 20170352703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'METHOD FOR FABRICATING AN ARRAY OF DIODES, IN PARTICULAR FOR A NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/365143 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365143
Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device Nov 29, 2016 Issued
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