Search

Bernarr E. Gregory

Examiner (ID: 11710, Phone: (571)272-6972 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
2202, 3646, 3648, 3642, 2766, 3662
Total Applications
4661
Issued Applications
4105
Pending Applications
272
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1418224 [patent_doc_number] => 06514832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Gunn diode, NRD guide Gunn oscillator, fabricating method of Gunn diode and structure for assembly of the same' [patent_app_type] => B1 [patent_app_number] => 09/541097 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 50 [patent_no_of_words] => 11783 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514832.pdf [firstpage_image] =>[orig_patent_app_number] => 09541097 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541097
Gunn diode, NRD guide Gunn oscillator, fabricating method of Gunn diode and structure for assembly of the same Mar 30, 2000 Issued
Array ( [id] => 1453695 [patent_doc_number] => 06461984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Semiconductor device using N2O plasma oxide and a method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/535156 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2614 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461984.pdf [firstpage_image] =>[orig_patent_app_number] => 09535156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535156
Semiconductor device using N2O plasma oxide and a method of fabricating the same Mar 23, 2000 Issued
Array ( [id] => 1458880 [patent_doc_number] => 06426289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method of fabricating a barrier layer associated with a conductor layer in damascene structures' [patent_app_type] => B1 [patent_app_number] => 09/534224 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3162 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426289.pdf [firstpage_image] =>[orig_patent_app_number] => 09534224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534224
Method of fabricating a barrier layer associated with a conductor layer in damascene structures Mar 23, 2000 Issued
Array ( [id] => 1514495 [patent_doc_number] => 06420234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Short channel length transistor and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/531127 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4163 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420234.pdf [firstpage_image] =>[orig_patent_app_number] => 09531127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531127
Short channel length transistor and method of fabricating the same Mar 16, 2000 Issued
Array ( [id] => 4271509 [patent_doc_number] => 06323116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Differential pair geometry for integrated circuit chip packages' [patent_app_type] => 1 [patent_app_number] => 9/487218 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3759 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323116.pdf [firstpage_image] =>[orig_patent_app_number] => 487218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487218
Differential pair geometry for integrated circuit chip packages Jan 18, 2000 Issued
Array ( [id] => 7643939 [patent_doc_number] => 06429099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Implementing contacts for bodies of semiconductor-on-insulator transistors' [patent_app_type] => B1 [patent_app_number] => 09/478037 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2476 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429099.pdf [firstpage_image] =>[orig_patent_app_number] => 09478037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478037
Implementing contacts for bodies of semiconductor-on-insulator transistors Jan 4, 2000 Issued
Array ( [id] => 1503495 [patent_doc_number] => 06465315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'MOS transistor with local channel compensation implant' [patent_app_type] => B1 [patent_app_number] => 09/476527 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465315.pdf [firstpage_image] =>[orig_patent_app_number] => 09476527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476527
MOS transistor with local channel compensation implant Jan 2, 2000 Issued
Array ( [id] => 1527981 [patent_doc_number] => 06479310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Method for testing a semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/476807 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479310.pdf [firstpage_image] =>[orig_patent_app_number] => 09476807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476807
Method for testing a semiconductor integrated circuit device Jan 2, 2000 Issued
Array ( [id] => 1274070 [patent_doc_number] => 06649520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier' [patent_app_type] => B1 [patent_app_number] => 09/461767 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2541 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649520.pdf [firstpage_image] =>[orig_patent_app_number] => 09461767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461767
Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier Dec 14, 1999 Issued
Array ( [id] => 1446633 [patent_doc_number] => 06368955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of polishing semiconductor structures using a two-step chemical mechanical planarization with slurry particles having different particle bulk densities' [patent_app_type] => B1 [patent_app_number] => 09/444817 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368955.pdf [firstpage_image] =>[orig_patent_app_number] => 09444817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/444817
Method of polishing semiconductor structures using a two-step chemical mechanical planarization with slurry particles having different particle bulk densities Nov 21, 1999 Issued
09/439557 FABRICATION METHOD FOR SELF-ALIGNED SILICIDE Nov 11, 1999 Abandoned
Array ( [id] => 1459653 [patent_doc_number] => 06391800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for patterning a substrate with photoresist' [patent_app_type] => B1 [patent_app_number] => 09/439177 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2711 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391800.pdf [firstpage_image] =>[orig_patent_app_number] => 09439177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439177
Method for patterning a substrate with photoresist Nov 11, 1999 Issued
09/435670 OXIDATIVE ANNEALING METHOD FOR FORMING ETCHED SPIN-ON-GLASS (SOG) PLANARIZING LAYER WITH UNIFORM ETCH PROFILE Nov 7, 1999 Abandoned
Array ( [id] => 4358773 [patent_doc_number] => 06255206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of forming gate electrode with titanium polycide structure' [patent_app_type] => 1 [patent_app_number] => 9/434647 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1874 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255206.pdf [firstpage_image] =>[orig_patent_app_number] => 434647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434647
Method of forming gate electrode with titanium polycide structure Nov 4, 1999 Issued
Array ( [id] => 4359014 [patent_doc_number] => 06291867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Zirconium and/or hafnium silicon-oxynitride gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/434205 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 19 [patent_no_of_words] => 6627 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291867.pdf [firstpage_image] =>[orig_patent_app_number] => 434205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434205
Zirconium and/or hafnium silicon-oxynitride gate dielectric Nov 3, 1999 Issued
Array ( [id] => 1534563 [patent_doc_number] => 06489210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method for forming dual gate in DRAM embedded with a logic circuit' [patent_app_type] => B1 [patent_app_number] => 09/432807 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4283 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489210.pdf [firstpage_image] =>[orig_patent_app_number] => 09432807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432807
Method for forming dual gate in DRAM embedded with a logic circuit Nov 2, 1999 Issued
Array ( [id] => 1372179 [patent_doc_number] => 06562723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Hybrid stack method for patterning source/drain areas' [patent_app_type] => B1 [patent_app_number] => 09/430160 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562723.pdf [firstpage_image] =>[orig_patent_app_number] => 09430160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430160
Hybrid stack method for patterning source/drain areas Oct 28, 1999 Issued
Array ( [id] => 4381736 [patent_doc_number] => 06294465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method for making integrated circuits having features with reduced critical dimensions' [patent_app_type] => 1 [patent_app_number] => 9/430147 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1778 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294465.pdf [firstpage_image] =>[orig_patent_app_number] => 430147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430147
Method for making integrated circuits having features with reduced critical dimensions Oct 28, 1999 Issued
Array ( [id] => 1500480 [patent_doc_number] => 06486067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure' [patent_app_type] => B1 [patent_app_number] => 09/429670 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2178 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486067.pdf [firstpage_image] =>[orig_patent_app_number] => 09429670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429670
Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure Oct 28, 1999 Issued
Array ( [id] => 1588840 [patent_doc_number] => 06482711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'InPSb/InAs BJT device and method of making' [patent_app_type] => B1 [patent_app_number] => 09/428820 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4447 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482711.pdf [firstpage_image] =>[orig_patent_app_number] => 09428820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428820
InPSb/InAs BJT device and method of making Oct 27, 1999 Issued
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