
Bernarr E. Gregory
Examiner (ID: 16577)
| Most Active Art Unit | 3648 |
| Art Unit(s) | 3642, 3646, 2202, 3662, 3648, 2766 |
| Total Applications | 4684 |
| Issued Applications | 4115 |
| Pending Applications | 277 |
| Abandoned Applications | 314 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9837704
[patent_doc_number] => 20150029784
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-29
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/334790
[patent_app_country] => US
[patent_app_date] => 2014-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 15129
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14334790
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/334790 | Semiconductor integrated circuit device | Jul 17, 2014 | Issued |
Array
(
[id] => 10375772
[patent_doc_number] => 20150260779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/335235
[patent_app_country] => US
[patent_app_date] => 2014-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7077
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14335235
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/335235 | SEMICONDUCTOR DEVICE | Jul 17, 2014 | Abandoned |
Array
(
[id] => 10925113
[patent_doc_number] => 20140328133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-06
[patent_title] => 'SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/334252
[patent_app_country] => US
[patent_app_date] => 2014-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8265
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14334252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/334252 | SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM | Jul 16, 2014 | Abandoned |
Array
(
[id] => 10512969
[patent_doc_number] => 09240550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-19
[patent_title] => 'Resistive memory element based on oxygen-doped amorphous carbon'
[patent_app_type] => utility
[patent_app_number] => 14/333806
[patent_app_country] => US
[patent_app_date] => 2014-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 8936
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333806
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/333806 | Resistive memory element based on oxygen-doped amorphous carbon | Jul 16, 2014 | Issued |
Array
(
[id] => 9863258
[patent_doc_number] => 20150043277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'Data Storage System with Dynamic Erase Block Grouping Mechanism and Method of Operation Thereof'
[patent_app_type] => utility
[patent_app_number] => 14/334350
[patent_app_country] => US
[patent_app_date] => 2014-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9010
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14334350
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/334350 | Data storage system with dynamic erase block grouping mechanism and method of operation thereof | Jul 16, 2014 | Issued |
Array
(
[id] => 10638221
[patent_doc_number] => 09355729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-31
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 14/334222
[patent_app_country] => US
[patent_app_date] => 2014-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 7052
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14334222
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/334222 | Non-volatile memory device | Jul 16, 2014 | Issued |
Array
(
[id] => 12213800
[patent_doc_number] => 09910607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-06
[patent_title] => 'Method of managing a memory, and a memory system'
[patent_app_type] => utility
[patent_app_number] => 14/332892
[patent_app_country] => US
[patent_app_date] => 2014-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 13633
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332892
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/332892 | Method of managing a memory, and a memory system | Jul 15, 2014 | Issued |
Array
(
[id] => 10617406
[patent_doc_number] => 09336852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-10
[patent_title] => 'Memory and memory system including the same'
[patent_app_type] => utility
[patent_app_number] => 14/333300
[patent_app_country] => US
[patent_app_date] => 2014-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5614
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333300
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/333300 | Memory and memory system including the same | Jul 15, 2014 | Issued |
Array
(
[id] => 10918209
[patent_doc_number] => 20140321228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-30
[patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER'
[patent_app_type] => utility
[patent_app_number] => 14/331436
[patent_app_country] => US
[patent_app_date] => 2014-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11538
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331436
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/331436 | Semiconductor device including plural chips stacked to each other | Jul 14, 2014 | Issued |
Array
(
[id] => 10659605
[patent_doc_number] => 20160005749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-07
[patent_title] => 'SERIES FERROELECTRIC NEGATIVE CAPACITOR FOR MULTIPLE TIME PROGRAMMABLE (MTP) DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/321593
[patent_app_country] => US
[patent_app_date] => 2014-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9210
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321593
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/321593 | SERIES FERROELECTRIC NEGATIVE CAPACITOR FOR MULTIPLE TIME PROGRAMMABLE (MTP) DEVICES | Jun 30, 2014 | Abandoned |
Array
(
[id] => 10495056
[patent_doc_number] => 20150380078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'MEMORY CHIP AND LAYOUT DESIGN FOR MANUFACTURING SAME'
[patent_app_type] => utility
[patent_app_number] => 14/317146
[patent_app_country] => US
[patent_app_date] => 2014-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 12750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317146
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/317146 | Memory chip and layout design for manufacturing same | Jun 26, 2014 | Issued |
Array
(
[id] => 10563288
[patent_doc_number] => 09286969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-15
[patent_title] => 'Low power sense amplifier for static random access memory'
[patent_app_type] => utility
[patent_app_number] => 14/317806
[patent_app_country] => US
[patent_app_date] => 2014-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8180
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317806
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/317806 | Low power sense amplifier for static random access memory | Jun 26, 2014 | Issued |
Array
(
[id] => 10495400
[patent_doc_number] => 20150380422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'Vertical Floating Gate NAND with Selectively Deposited ALD Metal Films'
[patent_app_type] => utility
[patent_app_number] => 14/314370
[patent_app_country] => US
[patent_app_date] => 2014-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7505
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314370
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/314370 | Vertical floating gate NAND with selectively deposited ALD metal films | Jun 24, 2014 | Issued |
Array
(
[id] => 10479179
[patent_doc_number] => 20150364196
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-17
[patent_title] => 'ARRAY FANOUT PASS TRANSISTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/305782
[patent_app_country] => US
[patent_app_date] => 2014-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8083
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305782
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/305782 | Array fanout pass transistor structure | Jun 15, 2014 | Issued |
Array
(
[id] => 10073238
[patent_doc_number] => 09111599
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-08-18
[patent_title] => 'Memory device'
[patent_app_type] => utility
[patent_app_number] => 14/300238
[patent_app_country] => US
[patent_app_date] => 2014-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3620
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 365
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300238
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/300238 | Memory device | Jun 9, 2014 | Issued |
Array
(
[id] => 13224975
[patent_doc_number] => 10126259
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-13
[patent_title] => Radio frequency identification (RFID) devices for detecting volatile substances
[patent_app_type] => utility
[patent_app_number] => 14/897772
[patent_app_country] => US
[patent_app_date] => 2014-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 8392
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14897772
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/897772 | Radio frequency identification (RFID) devices for detecting volatile substances | Jun 9, 2014 | Issued |
Array
(
[id] => 10066466
[patent_doc_number] => 09105321
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-08-11
[patent_title] => 'Memory device and driving circuit adopted by the memory device'
[patent_app_type] => utility
[patent_app_number] => 14/298506
[patent_app_country] => US
[patent_app_date] => 2014-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4725
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14298506
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/298506 | Memory device and driving circuit adopted by the memory device | Jun 5, 2014 | Issued |
Array
(
[id] => 9755418
[patent_doc_number] => 20140286119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION'
[patent_app_type] => utility
[patent_app_number] => 14/295320
[patent_app_country] => US
[patent_app_date] => 2014-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 25403
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14295320
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/295320 | Memory devices, systems and methods employing command/address calibration | Jun 2, 2014 | Issued |
Array
(
[id] => 10230724
[patent_doc_number] => 20150115718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-30
[patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE'
[patent_app_type] => utility
[patent_app_number] => 14/293326
[patent_app_country] => US
[patent_app_date] => 2014-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4984
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14293326
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/293326 | Semiconductor device and semiconductor module | Jun 1, 2014 | Issued |
Array
(
[id] => 9733373
[patent_doc_number] => 20140269081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS'
[patent_app_type] => utility
[patent_app_number] => 14/290224
[patent_app_country] => US
[patent_app_date] => 2014-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 19361
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290224
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/290224 | Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits | May 28, 2014 | Issued |