Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9952745 [patent_doc_number] => 09001546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => '3D structure for advanced SRAM design to avoid half-selected issue' [patent_app_type] => utility [patent_app_number] => 13/972988 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/972988
3D structure for advanced SRAM design to avoid half-selected issue Aug 21, 2013 Issued
Array ( [id] => 9382479 [patent_doc_number] => 20140085960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/973490 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16401 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13973490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/973490
Semiconductor memory device and electronic device Aug 21, 2013 Issued
Array ( [id] => 9190185 [patent_doc_number] => 20130329500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'NONVOLATILE MEMORY DEVICE, ERASING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/967455 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 18621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967455 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967455
Nonvolatile memory device, erasing method thereof, and memory system including the same Aug 14, 2013 Issued
Array ( [id] => 9287713 [patent_doc_number] => 08644053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Resistor thin film MTP memory' [patent_app_type] => utility [patent_app_number] => 13/953626 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 38 [patent_no_of_words] => 19863 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953626 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953626
Resistor thin film MTP memory Jul 28, 2013 Issued
Array ( [id] => 9712660 [patent_doc_number] => 08837245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Memory cell array latchup prevention' [patent_app_type] => utility [patent_app_number] => 13/949116 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6210 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949116
Memory cell array latchup prevention Jul 22, 2013 Issued
Array ( [id] => 9137274 [patent_doc_number] => 20130297989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'Memory Device Readout Using Multiple Sense Times' [patent_app_type] => utility [patent_app_number] => 13/936622 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936622 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/936622
Memory device readout using multiple sense times Jul 7, 2013 Issued
Array ( [id] => 9356859 [patent_doc_number] => 08675405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Method to reduce program disturbs in non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 13/920352 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5443 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920352 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/920352
Method to reduce program disturbs in non-volatile memory cells Jun 17, 2013 Issued
Array ( [id] => 9092736 [patent_doc_number] => 20130272047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED' [patent_app_type] => utility [patent_app_number] => 13/915338 [patent_app_country] => US [patent_app_date] => 2013-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11272 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13915338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/915338
Memory device from which dummy edge memory block is removed Jun 10, 2013 Issued
Array ( [id] => 10358331 [patent_doc_number] => 20150243336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'Decreased Switching Current in Spin-Transfer Torque Memory' [patent_app_type] => utility [patent_app_number] => 14/431607 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6114 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14431607 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/431607
Decreased switching current in spin-transfer torque memory Jun 9, 2013 Issued
Array ( [id] => 9300986 [patent_doc_number] => 08649222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Nonvolatile semiconductor memory device which transfers a plurality of voltages to memory cells and method of writing the same' [patent_app_type] => utility [patent_app_number] => 13/909286 [patent_app_country] => US [patent_app_date] => 2013-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 12106 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/909286
Nonvolatile semiconductor memory device which transfers a plurality of voltages to memory cells and method of writing the same Jun 3, 2013 Issued
Array ( [id] => 9064534 [patent_doc_number] => 20130256290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'WELDING POWER SUPPLY WITH DIGITAL CONTROL OF DUTY CYCLE' [patent_app_type] => utility [patent_app_number] => 13/899188 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899188 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/899188
Welding power supply with digital control of duty cycle May 20, 2013 Issued
Array ( [id] => 9014914 [patent_doc_number] => 20130229878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME' [patent_app_type] => utility [patent_app_number] => 13/847189 [patent_app_country] => US [patent_app_date] => 2013-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/847189
System and method for reducing pin-count of memory devices, and memory device testers for same Mar 18, 2013 Issued
Array ( [id] => 9558455 [patent_doc_number] => 20140176167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/845308 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845308
Semiconductor apparatus Mar 17, 2013 Issued
Array ( [id] => 8988378 [patent_doc_number] => 20130215659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/846276 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 15665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846276
LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME Mar 17, 2013 Abandoned
Array ( [id] => 9196761 [patent_doc_number] => 20130336076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'MEMORY DEVICE, OPERATION METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/833195 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833195
Memory device, operation method thereof, and memory system having the same Mar 14, 2013 Issued
Array ( [id] => 9203977 [patent_doc_number] => 20140003154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/832983 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832983
Semiconductor memory device Mar 14, 2013 Issued
Array ( [id] => 10047188 [patent_doc_number] => 09087587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Integrated circuits and methods for operating integrated circuits with non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/834019 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4429 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834019 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834019
Integrated circuits and methods for operating integrated circuits with non-volatile memory Mar 14, 2013 Issued
Array ( [id] => 9066992 [patent_doc_number] => 20130258748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'FUSE DATA READING CIRCUIT HAVING MULTIPLE READING MODES AND RELATED DEVICES, SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/835319 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835319 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835319
Fuse data reading circuit having multiple reading modes and related devices, systems and methods Mar 14, 2013 Issued
Array ( [id] => 9382521 [patent_doc_number] => 20140086002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DETECTION CLOCK PATTERN GENERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/828869 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13828869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/828869
Semiconductor memory device having detection clock patterns phase-inverted from each other and detection clock generating method thereof Mar 13, 2013 Issued
Array ( [id] => 9361889 [patent_doc_number] => 20140071762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/785501 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8244 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785501
Nonvolatile semiconductor memory device and method of manufacturing the same Mar 4, 2013 Issued
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