Search

Bernarr E. Gregory

Examiner (ID: 11710, Phone: (571)272-6972 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
2202, 3646, 3648, 3642, 2766, 3662
Total Applications
4661
Issued Applications
4105
Pending Applications
272
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1564949 [patent_doc_number] => 06339008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/429000 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3979 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339008.pdf [firstpage_image] =>[orig_patent_app_number] => 09429000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429000
Method of manufacturing a semiconductor memory device Oct 27, 1999 Issued
Array ( [id] => 1563132 [patent_doc_number] => 06362521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor ceramic and device using the same' [patent_app_type] => B1 [patent_app_number] => 09/427997 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362521.pdf [firstpage_image] =>[orig_patent_app_number] => 09427997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427997
Semiconductor ceramic and device using the same Oct 26, 1999 Issued
Array ( [id] => 4377367 [patent_doc_number] => 06303424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method for fabricating a buried bit line in a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/422577 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2287 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303424.pdf [firstpage_image] =>[orig_patent_app_number] => 422577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422577
Method for fabricating a buried bit line in a DRAM cell Oct 20, 1999 Issued
Array ( [id] => 4359000 [patent_doc_number] => 06291866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Zirconium and/or hafnium oxynitride gate dielectric' [patent_app_type] => 1 [patent_app_number] => 9/421837 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291866.pdf [firstpage_image] =>[orig_patent_app_number] => 421837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421837
Zirconium and/or hafnium oxynitride gate dielectric Oct 19, 1999 Issued
Array ( [id] => 1581307 [patent_doc_number] => 06423652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Post-processing treatment of low dielectric constant material' [patent_app_type] => B1 [patent_app_number] => 09/420960 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1983 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423652.pdf [firstpage_image] =>[orig_patent_app_number] => 09420960 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420960
Post-processing treatment of low dielectric constant material Oct 18, 1999 Issued
Array ( [id] => 4358152 [patent_doc_number] => 06255165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Nitride plug to reduce gate edge lifting' [patent_app_type] => 1 [patent_app_number] => 9/420220 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4277 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255165.pdf [firstpage_image] =>[orig_patent_app_number] => 420220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420220
Nitride plug to reduce gate edge lifting Oct 17, 1999 Issued
Array ( [id] => 1566001 [patent_doc_number] => 06376361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method to remove excess metal in the formation of damascene and dual interconnects' [patent_app_type] => B1 [patent_app_number] => 09/419510 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5032 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376361.pdf [firstpage_image] =>[orig_patent_app_number] => 09419510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419510
Method to remove excess metal in the formation of damascene and dual interconnects Oct 17, 1999 Issued
Array ( [id] => 4327273 [patent_doc_number] => 06319814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of fabricating dual damascene' [patent_app_type] => 1 [patent_app_number] => 9/417830 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2486 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319814.pdf [firstpage_image] =>[orig_patent_app_number] => 417830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417830
Method of fabricating dual damascene Oct 11, 1999 Issued
Array ( [id] => 1466889 [patent_doc_number] => 06458615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of fabricating micromachined structures and devices formed therefrom' [patent_app_type] => B1 [patent_app_number] => 09/409570 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 4984 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458615.pdf [firstpage_image] =>[orig_patent_app_number] => 09409570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409570
Method of fabricating micromachined structures and devices formed therefrom Sep 29, 1999 Issued
Array ( [id] => 1564854 [patent_doc_number] => 06338988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step' [patent_app_type] => B1 [patent_app_number] => 09/410280 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338988.pdf [firstpage_image] =>[orig_patent_app_number] => 09410280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410280
Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step Sep 29, 1999 Issued
Array ( [id] => 1581198 [patent_doc_number] => 06423627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method for forming memory array and periphery contacts using a same mask' [patent_app_type] => B1 [patent_app_number] => 09/407560 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3033 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423627.pdf [firstpage_image] =>[orig_patent_app_number] => 09407560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407560
Method for forming memory array and periphery contacts using a same mask Sep 27, 1999 Issued
Array ( [id] => 4304482 [patent_doc_number] => 06326317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for fabricating metal oxide semiconductor field effect transistor (MOSFET)' [patent_app_type] => 1 [patent_app_number] => 9/399680 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 3569 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326317.pdf [firstpage_image] =>[orig_patent_app_number] => 399680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399680
Method for fabricating metal oxide semiconductor field effect transistor (MOSFET) Sep 20, 1999 Issued
Array ( [id] => 1416994 [patent_doc_number] => 06509278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method of forming a semiconductor contact that includes selectively removing a Ti-containing layer from the surface' [patent_app_type] => B1 [patent_app_number] => 09/388660 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4759 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509278.pdf [firstpage_image] =>[orig_patent_app_number] => 09388660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388660
Method of forming a semiconductor contact that includes selectively removing a Ti-containing layer from the surface Sep 1, 1999 Issued
Array ( [id] => 1520733 [patent_doc_number] => 06413858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Barrier and electroplating seed layer' [patent_app_type] => B1 [patent_app_number] => 09/384347 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413858.pdf [firstpage_image] =>[orig_patent_app_number] => 09384347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384347
Barrier and electroplating seed layer Aug 26, 1999 Issued
Array ( [id] => 4188824 [patent_doc_number] => 06153510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor device and method for manufacturing the same, and semiconductor memory device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/383189 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 8853 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153510.pdf [firstpage_image] =>[orig_patent_app_number] => 383189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383189
Semiconductor device and method for manufacturing the same, and semiconductor memory device and method for manufacturing the same Aug 25, 1999 Issued
Array ( [id] => 4336033 [patent_doc_number] => 06333211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Process for manufacturing a premold type semiconductor package using support pins in the mold and external connector bumps' [patent_app_type] => 1 [patent_app_number] => 9/383577 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5003 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333211.pdf [firstpage_image] =>[orig_patent_app_number] => 383577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383577
Process for manufacturing a premold type semiconductor package using support pins in the mold and external connector bumps Aug 24, 1999 Issued
Array ( [id] => 4366385 [patent_doc_number] => 06274460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Defect gettering by induced stress' [patent_app_type] => 1 [patent_app_number] => 9/334987 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2305 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274460.pdf [firstpage_image] =>[orig_patent_app_number] => 334987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334987
Defect gettering by induced stress Jun 16, 1999 Issued
Array ( [id] => 4291706 [patent_doc_number] => 06180440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of fabricating a recessed-gate FET without producing voids in the gate metal' [patent_app_type] => 1 [patent_app_number] => 9/312220 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 1948 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180440.pdf [firstpage_image] =>[orig_patent_app_number] => 312220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312220
Method of fabricating a recessed-gate FET without producing voids in the gate metal May 13, 1999 Issued
Array ( [id] => 4188574 [patent_doc_number] => 06153494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash' [patent_app_type] => 1 [patent_app_number] => 9/310257 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4063 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153494.pdf [firstpage_image] =>[orig_patent_app_number] => 310257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310257
Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash May 11, 1999 Issued
Array ( [id] => 4097715 [patent_doc_number] => 06048761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method for manufacturing a semiconductor device with self-aligned protection diode' [patent_app_type] => 1 [patent_app_number] => 9/301690 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3469 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048761.pdf [firstpage_image] =>[orig_patent_app_number] => 301690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301690
Method for manufacturing a semiconductor device with self-aligned protection diode Apr 28, 1999 Issued
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