Bernarr E. Gregory

Array ( [id] => 9106124 [patent_doc_number] => 20130279256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits' [patent_app_type] => utility [patent_app_number] => 13/450294 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 19293 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8334253 [patent_doc_number] => 20120200959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'FLEXURE BASED SHOCK AND VIBRATION SENSOR FOR HEAD SUSPENSIONS IN HARD DISK DRIVES' [patent_app_type] => utility [patent_app_number] => 13/449679 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3483 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8877291 [patent_doc_number] => 08472264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/447491 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4707 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8669997 [patent_doc_number] => 20130044535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'REFERENCE CELL CIRCUIT AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/634292 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16680 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13634292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9066994 [patent_doc_number] => 20130258750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINATION ABILITY' [patent_app_type] => utility [patent_app_number] => 13/435000 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5168 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8847725 [patent_doc_number] => 08456915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Programming non-volatile storage with fast bit detection and verify skip' [patent_app_type] => utility [patent_app_number] => 13/436805 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 15506 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9505257 [patent_doc_number] => 08743580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Apparatus for high speed ROM cells' [patent_app_type] => utility [patent_app_number] => 13/436452 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8321 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10015839 [patent_doc_number] => 09058860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Methods and apparatus for synthesizing multi-port memory circuits' [patent_app_type] => utility [patent_app_number] => 13/434296 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10892 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9101124 [patent_doc_number] => 08565013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Storage element and storage device' [patent_app_type] => utility [patent_app_number] => 13/434478 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8015 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9628118 [patent_doc_number] => 08797807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Semiconductor memory and semiconductor memory control method' [patent_app_type] => utility [patent_app_number] => 13/432708 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8859989 [patent_doc_number] => 08462534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Memory module cutting off DM pad leakage current' [patent_app_type] => utility [patent_app_number] => 13/430860 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4365 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9553897 [patent_doc_number] => 08760957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Non-volatile memory and method having a memory array with a high-speed, short bit-line portion' [patent_app_type] => utility [patent_app_number] => 13/431670 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6665 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8428563 [patent_doc_number] => 20120250437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/431654 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9484757 [patent_doc_number] => 08730715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Tamper-resistant MRAM utilizing chemical alteration' [patent_app_type] => utility [patent_app_number] => 13/429692 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9217325 [patent_doc_number] => 08630130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Memory circuit, memory unit, and signal processing circuit' [patent_app_type] => utility [patent_app_number] => 13/429574 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 25892 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9052975 [patent_doc_number] => 20130250689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 13/430494 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 26005 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9553885 [patent_doc_number] => 08760945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Memory devices, systems and methods employing command/address calibration' [patent_app_type] => utility [patent_app_number] => 13/430438 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 25382 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9650373 [patent_doc_number] => 08804399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Multi-function resistance change memory cells and apparatuses including the same' [patent_app_type] => utility [patent_app_number] => 13/428944 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 9788 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9442480 [patent_doc_number] => 08711602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/428246 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 6655 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8475819 [patent_doc_number] => 20120275226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 13/428384 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5813 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428384 [rel_patent_id] =>[rel_patent_doc_number] =>)