Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9052935 [patent_doc_number] => 20130250649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/428256 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5973 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428256 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428256
Semiconductor device and method for controlling the same Mar 22, 2012 Issued
Array ( [id] => 9377286 [patent_doc_number] => 08681556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/425704 [patent_app_country] => US [patent_app_date] => 2012-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6865 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13425704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/425704
Non-volatile semiconductor memory device Mar 20, 2012 Issued
Array ( [id] => 9705671 [patent_doc_number] => 08830751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/424812 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424812
Semiconductor memory device Mar 19, 2012 Issued
Array ( [id] => 9664075 [patent_doc_number] => 08811072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Magnetoresistive random access memory (MRAM) package including a multilayer magnetic security structure' [patent_app_type] => utility [patent_app_number] => 13/419109 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 11948 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419109
Magnetoresistive random access memory (MRAM) package including a multilayer magnetic security structure Mar 12, 2012 Issued
Array ( [id] => 8677007 [patent_doc_number] => 08385130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Semiconductor memory device which stores plural data in a cell' [patent_app_type] => utility [patent_app_number] => 13/413779 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 105 [patent_no_of_words] => 39127 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413779 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/413779
Semiconductor memory device which stores plural data in a cell Mar 6, 2012 Issued
Array ( [id] => 8250832 [patent_doc_number] => 20120155148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'RESISTANCE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/407001 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20120155148.pdf [firstpage_image] =>[orig_patent_app_number] => 13407001 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407001
Resistance change memory device Feb 27, 2012 Issued
Array ( [id] => 9150551 [patent_doc_number] => 20130305074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'PROTOCOL FOR MEMORY POWER-MODE CONTROL' [patent_app_type] => utility [patent_app_number] => 13/980826 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4509 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980826 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980826
Protocol for memory power-mode control Feb 14, 2012 Issued
Array ( [id] => 9160094 [patent_doc_number] => 20130308371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'METHOD FOR READING DATA FROM NONVOLATILE STORAGE ELEMENT, AND NONVOLATILE STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/982280 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21261 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13982280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/982280
Method for reading data from nonvolatile storage element, and nonvolatile storage device Jan 30, 2012 Issued
Array ( [id] => 9141865 [patent_doc_number] => 08582340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Word line and power conductor within a metal layer of a memory cell' [patent_app_type] => utility [patent_app_number] => 13/348838 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2381 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348838 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348838
Word line and power conductor within a metal layer of a memory cell Jan 11, 2012 Issued
Array ( [id] => 8182530 [patent_doc_number] => 20120113705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/348895 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4634 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20120113705.pdf [firstpage_image] =>[orig_patent_app_number] => 13348895 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348895
Configurable inputs and outputs for memory stacking system and method Jan 11, 2012 Issued
Array ( [id] => 8300256 [patent_doc_number] => 20120182815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices' [patent_app_type] => utility [patent_app_number] => 13/348672 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9661 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348672
Memory devices having controllers that divide command signals into two signals and systems including such memory devices Jan 11, 2012 Issued
Array ( [id] => 8288521 [patent_doc_number] => 20120176841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Flexible 2T-Based Fuzzy and Certain Matching Arrays' [patent_app_type] => utility [patent_app_number] => 13/347913 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6536 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347913
Flexible 2T-based fuzzy and certain matching arrays Jan 10, 2012 Issued
Array ( [id] => 9256066 [patent_doc_number] => 08619493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Flexible memory operations in NAND flash devices' [patent_app_type] => utility [patent_app_number] => 13/348107 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 24836 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348107
Flexible memory operations in NAND flash devices Jan 10, 2012 Issued
Array ( [id] => 9415244 [patent_doc_number] => 08699290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Semiconductor device and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/347527 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347527
Semiconductor device and method for forming the same Jan 9, 2012 Issued
Array ( [id] => 9498323 [patent_doc_number] => 08737152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Semiconductor memory device and method of testing the same' [patent_app_type] => utility [patent_app_number] => 13/347584 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5385 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347584
Semiconductor memory device and method of testing the same Jan 9, 2012 Issued
Array ( [id] => 8300269 [patent_doc_number] => 20120182822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER' [patent_app_type] => utility [patent_app_number] => 13/347542 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12527 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347542
Semiconductor device including plural chips stacked to each other Jan 9, 2012 Issued
Array ( [id] => 8300219 [patent_doc_number] => 20120182778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER' [patent_app_type] => utility [patent_app_number] => 13/347521 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11868 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347521
Semiconductor device including plural chips stacked to each other Jan 9, 2012 Issued
Array ( [id] => 8798328 [patent_doc_number] => 08437207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Apparatus for measuring data setup/hold time' [patent_app_type] => utility [patent_app_number] => 13/346308 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4408 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13346308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/346308
Apparatus for measuring data setup/hold time Jan 8, 2012 Issued
Array ( [id] => 9087776 [patent_doc_number] => 08559211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Phase change memory device' [patent_app_type] => utility [patent_app_number] => 13/338950 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 40 [patent_no_of_words] => 14484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13338950 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338950
Phase change memory device Dec 27, 2011 Issued
Array ( [id] => 9210823 [patent_doc_number] => 20140010000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'APPARATUS AND METHOD FOR IMPROVING POWER DELIVERY IN A MEMORY, SUCH AS, A RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 13/976858 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976858
Apparatus and method for improving power delivery in a memory, such as, a random access memory Dec 27, 2011 Issued
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