Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10502212 [patent_doc_number] => 09230614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Separate microchannel voltage domains in stacked memory architecture' [patent_app_type] => utility [patent_app_number] => 13/977404 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6329 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977404 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977404
Separate microchannel voltage domains in stacked memory architecture Dec 22, 2011 Issued
Array ( [id] => 10833074 [patent_doc_number] => 08861253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Variable resistance device, semiconductor device including the variable resistance device, and method of operating the semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/313720 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 14911 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313720
Variable resistance device, semiconductor device including the variable resistance device, and method of operating the semiconductor device Dec 6, 2011 Issued
Array ( [id] => 8798306 [patent_doc_number] => 08437184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-07 [patent_title] => 'Method of controlling a vertical dual-gate dynamic random access memory' [patent_app_type] => utility [patent_app_number] => 13/312074 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2967 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/312074
Method of controlling a vertical dual-gate dynamic random access memory Dec 5, 2011 Issued
Array ( [id] => 8852288 [patent_doc_number] => 20130141963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'Methods and Apparatus for FinFET SRAM Cells' [patent_app_type] => utility [patent_app_number] => 13/312828 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/312828
Methods and apparatus for FinFET SRAM cells Dec 5, 2011 Issued
Array ( [id] => 9403175 [patent_doc_number] => 08693235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Methods and apparatus for finFET SRAM arrays in integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/312810 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/312810
Methods and apparatus for finFET SRAM arrays in integrated circuits Dec 5, 2011 Issued
Array ( [id] => 9484761 [patent_doc_number] => 08730719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'MRAM with metal gate write conductors' [patent_app_type] => utility [patent_app_number] => 13/311470 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 2235 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311470
MRAM with metal gate write conductors Dec 4, 2011 Issued
Array ( [id] => 10833079 [patent_doc_number] => 08861257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Nonvolatile memory element, manufacturing method thereof, nonvolatile memory device, and design support method for nonvolatile memory element' [patent_app_type] => utility [patent_app_number] => 13/634700 [patent_app_country] => US [patent_app_date] => 2011-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 50 [patent_no_of_words] => 22901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13634700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/634700
Nonvolatile memory element, manufacturing method thereof, nonvolatile memory device, and design support method for nonvolatile memory element Nov 23, 2011 Issued
Array ( [id] => 8611266 [patent_doc_number] => 20130016578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'POWER SUPPLY SYSTEM FOR MEMORIES' [patent_app_type] => utility [patent_app_number] => 13/302940 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1090 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302940 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302940
Power supply system for memories Nov 21, 2011 Issued
Array ( [id] => 8207717 [patent_doc_number] => 20120127814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE PERFORMING STRESS TEST' [patent_app_type] => utility [patent_app_number] => 13/302772 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127814.pdf [firstpage_image] =>[orig_patent_app_number] => 13302772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302772
Semiconductor device performing stress test Nov 21, 2011 Issued
Array ( [id] => 8922435 [patent_doc_number] => 08488378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/301948 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301948 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301948
Nonvolatile semiconductor memory device Nov 21, 2011 Issued
Array ( [id] => 8219427 [patent_doc_number] => 20120134197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'MEMORY CELL AND MEMORY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/300688 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6392 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13300688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/300688
Memory cell and memory device using the same Nov 20, 2011 Issued
Array ( [id] => 8957478 [patent_doc_number] => 08503264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Reducing power consumption in a segmented memory' [patent_app_type] => utility [patent_app_number] => 13/300512 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12526 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13300512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/300512
Reducing power consumption in a segmented memory Nov 17, 2011 Issued
Array ( [id] => 8820010 [patent_doc_number] => 20130121055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'WORD LINE DRIVER CELL LAYOUT FOR SRAM AND OTHER SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/297296 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297296 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297296
Word line driver cell layout for SRAM and other semiconductor devices Nov 15, 2011 Issued
Array ( [id] => 8195349 [patent_doc_number] => 20120120735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/297960 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9968 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120735.pdf [firstpage_image] =>[orig_patent_app_number] => 13297960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297960
SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF Nov 15, 2011 Abandoned
Array ( [id] => 8820020 [patent_doc_number] => 20130121065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM' [patent_app_type] => utility [patent_app_number] => 13/296724 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296724
Dynamic wordline assist scheme to improve performance tradeoff in SRAM Nov 14, 2011 Issued
Array ( [id] => 8195391 [patent_doc_number] => 20120120752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Dual-Port Semiconductor Memory and First-In First-Out (FIFO) Memory Having Electrically Floating Body Transistor' [patent_app_type] => utility [patent_app_number] => 13/296402 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 31619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120752.pdf [firstpage_image] =>[orig_patent_app_number] => 13296402 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296402
Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor Nov 14, 2011 Issued
Array ( [id] => 8820013 [patent_doc_number] => 20130121057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'RESISTOR THIN FILM MTP MEMORY' [patent_app_type] => utility [patent_app_number] => 13/296628 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296628 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296628
Resistor thin film MTP memory Nov 14, 2011 Issued
Array ( [id] => 8195346 [patent_doc_number] => 20120120733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME' [patent_app_type] => utility [patent_app_number] => 13/295484 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13272 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120733.pdf [firstpage_image] =>[orig_patent_app_number] => 13295484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/295484
Semiconductor device including fuse array and method of operation the same Nov 13, 2011 Issued
Array ( [id] => 8820034 [patent_doc_number] => 20130121079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'NOR FLAH MEMORY CELL AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/295102 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3829 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13295102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/295102
NOR FLAH MEMORY CELL AND STRUCTURE THEREOF Nov 13, 2011 Abandoned
Array ( [id] => 9168182 [patent_doc_number] => 08593866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Systems and methods for operating multi-bank nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 13/294880 [patent_app_country] => US [patent_app_date] => 2011-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 14966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294880 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/294880
Systems and methods for operating multi-bank nonvolatile memory Nov 10, 2011 Issued
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