Bernarr E. Gregory

Array ( [id] => 8584628 [patent_doc_number] => 20130003449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'DESELECT DRIVERS FOR A MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/173068 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9217329 [patent_doc_number] => 08630135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/172958 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 6284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8207712 [patent_doc_number] => 20120127809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'PRECHARGE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/171850 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4554 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127809.pdf [firstpage_image] =>[orig_patent_app_number] => 13171850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8803602 [patent_doc_number] => 08441881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-14 [patent_title] => 'Tracking for read and inverse write back of a group of thyristor-based memory cells' [patent_app_type] => utility [patent_app_number] => 13/172630 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7708839 [patent_doc_number] => 20120002464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SEMICONDUCTOR DEVICE EQUIPPED WITH A PLURALITY OF MEMORY BANKS AND TEST METHOD OF THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/172252 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5874 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9128651 [patent_doc_number] => 08576607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-05 [patent_title] => 'Hybrid memory cell array and operations thereof' [patent_app_type] => utility [patent_app_number] => 13/172702 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9276 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8584663 [patent_doc_number] => 20130003484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'PARTIAL WRITE ON A LOW POWER MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/172592 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6828 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8910906 [patent_doc_number] => 08482978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-09 [patent_title] => 'Estimation of memory cell read thresholds by sampling inside programming level distribution intervals' [patent_app_type] => utility [patent_app_number] => 13/170202 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7583 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8584616 [patent_doc_number] => 20130003437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Multilayer Cross-Point Memory Array Having Reduced Disturb Susceptibility' [patent_app_type] => utility [patent_app_number] => 13/171350 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11832 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8714713 [patent_doc_number] => 08400859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Dynamic random access memory (DRAM) refresh' [patent_app_type] => utility [patent_app_number] => 13/169596 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3251 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13169596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7482729 [patent_doc_number] => 20110249499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same' [patent_app_type] => utility [patent_app_number] => 13/166291 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 14361 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20110249499.pdf [firstpage_image] =>[orig_patent_app_number] => 13166291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7661417 [patent_doc_number] => 20110310686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies' [patent_app_type] => utility [patent_app_number] => 13/165713 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9696 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20110310686.pdf [firstpage_image] =>[orig_patent_app_number] => 13165713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8068283 [patent_doc_number] => 20110242890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA' [patent_app_type] => utility [patent_app_number] => 13/158508 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 29341 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242890.pdf [firstpage_image] =>[orig_patent_app_number] => 13158508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7485108 [patent_doc_number] => 20110235412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'CONTROLLING AC DISTURBANCE WHILE PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 13/156763 [patent_app_country] => US [patent_app_date] => 2011-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235412.pdf [firstpage_image] =>[orig_patent_app_number] => 13156763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8544915 [patent_doc_number] => 08320212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Voltage stabilization circuit and semiconductor memory apparatus using the same' [patent_app_type] => utility [patent_app_number] => 13/155901 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020433 [patent_doc_number] => 20110225438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES' [patent_app_type] => utility [patent_app_number] => 13/115149 [patent_app_country] => US [patent_app_date] => 2011-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4143 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225438.pdf [firstpage_image] =>[orig_patent_app_number] => 13115149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6013234 [patent_doc_number] => 20110222362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/112706 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5207 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20110222362.pdf [firstpage_image] =>[orig_patent_app_number] => 13112706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8341613 [patent_doc_number] => 08243544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Reduction of fusible links and associated circuitry on memory dies' [patent_app_type] => utility [patent_app_number] => 13/110809 [patent_app_country] => US [patent_app_date] => 2011-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 6611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13110809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8258821 [patent_doc_number] => 08208322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Non-volatile memory control' [patent_app_type] => utility [patent_app_number] => 13/108477 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13108477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8423204 [patent_doc_number] => 08279696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/102295 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 6308 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102295 [rel_patent_id] =>[rel_patent_doc_number] =>)