
Bernarr E. Gregory
Examiner (ID: 16577)
| Most Active Art Unit | 3648 |
| Art Unit(s) | 3642, 3646, 2202, 3662, 3648, 2766 |
| Total Applications | 4684 |
| Issued Applications | 4115 |
| Pending Applications | 277 |
| Abandoned Applications | 314 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9010931
[patent_doc_number] => 08526242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Flash memory and fabrication method and operation method for the same'
[patent_app_type] => utility
[patent_app_number] => 13/321120
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13321120
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/321120 | Flash memory and fabrication method and operation method for the same | Mar 6, 2011 | Issued |
Array
(
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[patent_doc_number] => 08750015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-10
[patent_title] => 'Integrated circuit comprising a FRAM memory and method for granting read-access to a FRAM memory'
[patent_app_type] => utility
[patent_app_number] => 13/025878
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[patent_app_date] => 2011-02-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025878 | Integrated circuit comprising a FRAM memory and method for granting read-access to a FRAM memory | Feb 10, 2011 | Issued |
Array
(
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[patent_issue_date] => 2012-04-03
[patent_title] => 'Memory structure having volatile and non-volatile memory portions'
[patent_app_type] => utility
[patent_app_number] => 13/026052
[patent_app_country] => US
[patent_app_date] => 2011-02-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/026052 | Memory structure having volatile and non-volatile memory portions | Feb 10, 2011 | Issued |
Array
(
[id] => 8579239
[patent_doc_number] => 08345459
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[patent_kind] => B2
[patent_issue_date] => 2013-01-01
[patent_title] => 'Architecture to facilitate reuse in multiple applications'
[patent_app_type] => utility
[patent_app_number] => 13/024474
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/024474 | Architecture to facilitate reuse in multiple applications | Feb 9, 2011 | Issued |
Array
(
[id] => 7802298
[patent_doc_number] => 08130574
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[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Error detection on programmable logic resources'
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[patent_app_number] => 13/024666
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/024666 | Error detection on programmable logic resources | Feb 9, 2011 | Issued |
Array
(
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[patent_doc_number] => 08553466
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[patent_kind] => B2
[patent_issue_date] => 2013-10-08
[patent_title] => 'Non-volatile memory device, erasing method thereof, and memory system including the same'
[patent_app_type] => utility
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Array
(
[id] => 6060610
[patent_doc_number] => 20110199808
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[patent_issue_date] => 2011-08-18
[patent_title] => 'MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED'
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[pdf_file] => publications/A1/0199/20110199808.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/023738 | Memory device from which dummy edge memory block is removed | Feb 8, 2011 | Issued |
Array
(
[id] => 8334371
[patent_doc_number] => 20120201074
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[patent_issue_date] => 2012-08-09
[patent_title] => 'Magnetic Random Access Memory Devices Configured for Self-Referenced Read Operation'
[patent_app_type] => utility
[patent_app_number] => 13/023442
[patent_app_country] => US
[patent_app_date] => 2011-02-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/023442 | Magnetic random access memory devices configured for self-referenced read operation | Feb 7, 2011 | Issued |
Array
(
[id] => 8714724
[patent_doc_number] => 08400869
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[patent_issue_date] => 2013-03-19
[patent_title] => 'Semiconductor memory module'
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Array
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[id] => 6163456
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[patent_issue_date] => 2011-08-11
[patent_title] => 'METHOD OF PROGRAMMING MEMORY CELLS FOR A NON-VOLATILE MEMORY DEVICE'
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[patent_app_number] => 13/022688
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[firstpage_image] =>[orig_patent_app_number] => 13022688
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/022688 | Method of programming memory cells for a non-volatile memory device | Feb 7, 2011 | Issued |
Array
(
[id] => 8204651
[patent_doc_number] => 08189411
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[patent_issue_date] => 2012-05-29
[patent_title] => 'Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof'
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[patent_app_number] => 13/008314
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Array
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Array
(
[id] => 5942537
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[patent_title] => 'TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY'
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Array
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[patent_title] => 'Memory core and semiconductor memory device having the same'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974424 | Three-terminal ovonic threshold switch as a current driver in a phase change memory | Dec 20, 2010 | Issued |
Array
(
[id] => 7719054
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Array
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