Bernarr E. Gregory

Array ( [id] => 5874021 [patent_doc_number] => 20020048858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'METHODS OF T-GATE FABRICATION USING A HYBRID RESIST' [patent_app_type] => new [patent_app_number] => 09/299267 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3684 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048858.pdf [firstpage_image] =>[orig_patent_app_number] => 09299267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585433 [patent_doc_number] => 06358796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation' [patent_app_type] => B1 [patent_app_number] => 09/292360 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 4154 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358796.pdf [firstpage_image] =>[orig_patent_app_number] => 09292360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318753 [patent_doc_number] => 06248639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Electrostatic discharge protection circuit and transistor' [patent_app_type] => 1 [patent_app_number] => 9/290037 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3030 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248639.pdf [firstpage_image] =>[orig_patent_app_number] => 290037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1494918 [patent_doc_number] => 06403440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for fabricating a stacked capacitor in a semiconductor configuration, and stacked capacitor fabricated by this method' [patent_app_type] => B1 [patent_app_number] => 09/285897 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3296 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403440.pdf [firstpage_image] =>[orig_patent_app_number] => 09285897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318873 [patent_doc_number] => 06248648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method of breaking and separating a wafer into die using a multi-radii dome' [patent_app_type] => 1 [patent_app_number] => 9/280957 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4251 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248648.pdf [firstpage_image] =>[orig_patent_app_number] => 280957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4083632 [patent_doc_number] => 06162668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of manufacturing a semiconductor device having a lightly doped contact impurity region surrounding a highly doped contact impurity region' [patent_app_type] => 1 [patent_app_number] => 9/260737 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5162 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162668.pdf [firstpage_image] =>[orig_patent_app_number] => 260737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4275138 [patent_doc_number] => 06281060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of manufacturing a semiconductor device containing a BiCMOS circuit' [patent_app_type] => 1 [patent_app_number] => 9/257507 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 11566 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281060.pdf [firstpage_image] =>[orig_patent_app_number] => 257507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317708 [patent_doc_number] => 06316797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Scalable lead zirconium titanate(PZT) thin film material and deposition method, and ferroelectric memory device structures comprising such thin film material' [patent_app_type] => 1 [patent_app_number] => 9/251890 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 10972 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316797.pdf [firstpage_image] =>[orig_patent_app_number] => 251890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258932 [patent_doc_number] => 06258672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of fabricating an ESD protection device' [patent_app_type] => 1 [patent_app_number] => 9/252630 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3771 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258672.pdf [firstpage_image] =>[orig_patent_app_number] => 252630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359202 [patent_doc_number] => 06291880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor device including an integrally molded lead frame' [patent_app_type] => 1 [patent_app_number] => 9/248000 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3315 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291880.pdf [firstpage_image] =>[orig_patent_app_number] => 248000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523825 [patent_doc_number] => 06352944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of depositing an aluminum nitride comprising layer over a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/248197 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2148 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352944.pdf [firstpage_image] =>[orig_patent_app_number] => 09248197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416213 [patent_doc_number] => 06518160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method of manufacturing connection components using a plasma patterned mask' [patent_app_type] => B1 [patent_app_number] => 09/245227 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 6105 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518160.pdf [firstpage_image] =>[orig_patent_app_number] => 09245227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293988 [patent_doc_number] => 06197667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Structure and method for manufacturing Group III-V composite Schottky contacts enhanced by a sulphur fluoride/phosphorus fluoride layer' [patent_app_type] => 1 [patent_app_number] => 9/244290 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197667.pdf [firstpage_image] =>[orig_patent_app_number] => 244290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367003 [patent_doc_number] => 06274503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Etching method for doped polysilicon layer' [patent_app_type] => 1 [patent_app_number] => 9/241757 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3064 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274503.pdf [firstpage_image] =>[orig_patent_app_number] => 241757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367084 [patent_doc_number] => 06274509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Global planarization method for inter-layer-dielectric and inter-metal dielectric' [patent_app_type] => 1 [patent_app_number] => 9/239457 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3376 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274509.pdf [firstpage_image] =>[orig_patent_app_number] => 239457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359383 [patent_doc_number] => 06291893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Power semiconductor device for \"flip-chip\" connections' [patent_app_type] => 1 [patent_app_number] => 9/237407 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1846 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291893.pdf [firstpage_image] =>[orig_patent_app_number] => 237407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405425 [patent_doc_number] => 06232183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for fabricating a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/227680 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232183.pdf [firstpage_image] =>[orig_patent_app_number] => 227680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7028102 [patent_doc_number] => 20010014481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'DUAL TOX TRENCH DRAM STRUCTURES AND PROCESS USING V-GROOVE' [patent_app_type] => new [patent_app_number] => 09/225127 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4263 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014481.pdf [firstpage_image] =>[orig_patent_app_number] => 09225127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359368 [patent_doc_number] => 06291892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor package that includes a shallow metal basin surrounded by an insulator frame' [patent_app_type] => 1 [patent_app_number] => 9/224297 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6816 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291892.pdf [firstpage_image] =>[orig_patent_app_number] => 224297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4275354 [patent_doc_number] => 06307258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Open-cavity semiconductor die package' [patent_app_type] => 1 [patent_app_number] => 9/218180 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5311 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307258.pdf [firstpage_image] =>[orig_patent_app_number] => 218180 [rel_patent_id] =>[rel_patent_doc_number] =>)