Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4474732 [patent_doc_number] => 07944769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-17 [patent_title] => 'System for power-on detection' [patent_app_type] => utility [patent_app_number] => 12/579274 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944769.pdf [firstpage_image] =>[orig_patent_app_number] => 12579274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579274
System for power-on detection Oct 13, 2009 Issued
Array ( [id] => 6470617 [patent_doc_number] => 20100091597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/578974 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091597.pdf [firstpage_image] =>[orig_patent_app_number] => 12578974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578974
SEMICONDUCTOR DEVICE Oct 13, 2009 Abandoned
Array ( [id] => 6249749 [patent_doc_number] => 20100027362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE FOR LOW VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/578358 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12932 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027362.pdf [firstpage_image] =>[orig_patent_app_number] => 12578358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578358
Semiconductor memory device for low voltage Oct 12, 2009 Issued
Array ( [id] => 6249762 [patent_doc_number] => 20100027369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/577365 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14184 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027369.pdf [firstpage_image] =>[orig_patent_app_number] => 12577365 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577365
Semiconductor integrated circuit device Oct 11, 2009 Issued
Array ( [id] => 7516631 [patent_doc_number] => 08040711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Apparatus and methods for optically-coupled memory systems' [patent_app_type] => utility [patent_app_number] => 12/577015 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040711.pdf [firstpage_image] =>[orig_patent_app_number] => 12577015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577015
Apparatus and methods for optically-coupled memory systems Oct 8, 2009 Issued
Array ( [id] => 4467987 [patent_doc_number] => 07936633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Circuit and method of generating voltage of semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/575663 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3635 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936633.pdf [firstpage_image] =>[orig_patent_app_number] => 12575663 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575663
Circuit and method of generating voltage of semiconductor memory apparatus Oct 7, 2009 Issued
Array ( [id] => 4435930 [patent_doc_number] => 07969794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'One-transistor type DRAM' [patent_app_type] => utility [patent_app_number] => 12/575343 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9160 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969794.pdf [firstpage_image] =>[orig_patent_app_number] => 12575343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575343
One-transistor type DRAM Oct 6, 2009 Issued
Array ( [id] => 6467601 [patent_doc_number] => 20100007377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE' [patent_app_type] => utility [patent_app_number] => 12/564789 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14038 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20100007377.pdf [firstpage_image] =>[orig_patent_app_number] => 12564789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564789
Method and system for a serial peripheral interface Sep 21, 2009 Issued
Array ( [id] => 6605644 [patent_doc_number] => 20100002485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/559373 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002485.pdf [firstpage_image] =>[orig_patent_app_number] => 12559373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559373
Configurable inputs and outputs for memory stacking system and method Sep 13, 2009 Issued
Array ( [id] => 8039803 [patent_doc_number] => 20120069635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'CAPACITY AND DENSITY ENHANCEMENT CIRCUIT FOR SUB-THRESHOLD MEMORY UNIT ARRAY' [patent_app_type] => utility [patent_app_number] => 13/322114 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3662 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069635.pdf [firstpage_image] =>[orig_patent_app_number] => 13322114 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/322114
Capacity and density enhancement circuit for sub-threshold memory unit array Aug 17, 2009 Issued
Array ( [id] => 5366232 [patent_doc_number] => 20090303791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Semiconductor Memory Device for Storing Multivalued Data' [patent_app_type] => utility [patent_app_number] => 12/541040 [patent_app_country] => US [patent_app_date] => 2009-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 29197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303791.pdf [firstpage_image] =>[orig_patent_app_number] => 12541040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541040
Semiconductor memory device for storing multivalued data Aug 12, 2009 Issued
Array ( [id] => 7536492 [patent_doc_number] => 08050131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'System and memory for sequential multi-plane page memory operations' [patent_app_type] => utility [patent_app_number] => 12/534586 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5552 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/050/08050131.pdf [firstpage_image] =>[orig_patent_app_number] => 12534586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534586
System and memory for sequential multi-plane page memory operations Aug 2, 2009 Issued
Array ( [id] => 5489371 [patent_doc_number] => 20090290442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES' [patent_app_type] => utility [patent_app_number] => 12/510134 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9692 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290442.pdf [firstpage_image] =>[orig_patent_app_number] => 12510134 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510134
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies Jul 26, 2009 Issued
Array ( [id] => 5317708 [patent_doc_number] => 20090282306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES' [patent_app_type] => utility [patent_app_number] => 12/503637 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282306.pdf [firstpage_image] =>[orig_patent_app_number] => 12503637 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503637
Error detection on programmable logic resources Jul 14, 2009 Issued
Array ( [id] => 6459637 [patent_doc_number] => 20100039878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'CIRCUIT AND METHOD FOR GENERATING DATA OUTPUT CONTROL SIGNAL FOR SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/502436 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5670 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20100039878.pdf [firstpage_image] =>[orig_patent_app_number] => 12502436 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502436
Circuit and method for generating data output control signal for semiconductor integrated circuit Jul 13, 2009 Issued
Array ( [id] => 5556965 [patent_doc_number] => 20090268542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/500023 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5208 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20090268542.pdf [firstpage_image] =>[orig_patent_app_number] => 12500023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500023
Semiconductor memory device Jul 8, 2009 Issued
Array ( [id] => 4438794 [patent_doc_number] => 07898868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Multi-state memory' [patent_app_type] => utility [patent_app_number] => 12/499581 [patent_app_country] => US [patent_app_date] => 2009-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 16492 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898868.pdf [firstpage_image] =>[orig_patent_app_number] => 12499581 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499581
Multi-state memory Jul 7, 2009 Issued
Array ( [id] => 7536488 [patent_doc_number] => 08050127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/494844 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3636 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/050/08050127.pdf [firstpage_image] =>[orig_patent_app_number] => 12494844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494844
Semiconductor memory device Jun 29, 2009 Issued
Array ( [id] => 6571500 [patent_doc_number] => 20100290304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/494815 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3570 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290304.pdf [firstpage_image] =>[orig_patent_app_number] => 12494815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494815
Voltage stabilization circuit and semiconductor memory apparatus using the same Jun 29, 2009 Issued
Array ( [id] => 4531829 [patent_doc_number] => 07952948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/495026 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2261 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952948.pdf [firstpage_image] =>[orig_patent_app_number] => 12495026 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495026
Semiconductor memory apparatus Jun 29, 2009 Issued
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