Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7980089 [patent_doc_number] => 08072797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'SRAM cell without dedicated access transistors' [patent_app_type] => utility [patent_app_number] => 12/494908 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 8641 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072797.pdf [firstpage_image] =>[orig_patent_app_number] => 12494908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494908
SRAM cell without dedicated access transistors Jun 29, 2009 Issued
Array ( [id] => 6337760 [patent_doc_number] => 20100329054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Memory Built-In Self-Characterization' [patent_app_type] => utility [patent_app_number] => 12/494718 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329054.pdf [firstpage_image] =>[orig_patent_app_number] => 12494718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494718
Memory built-in self-characterization Jun 29, 2009 Issued
Array ( [id] => 7516671 [patent_doc_number] => 08040751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/493448 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7961 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040751.pdf [firstpage_image] =>[orig_patent_app_number] => 12493448 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493448
Semiconductor memory device Jun 28, 2009 Issued
Array ( [id] => 4541081 [patent_doc_number] => 07872935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Memory cells with power switch circuit for improved low voltage operation' [patent_app_type] => utility [patent_app_number] => 12/492879 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6295 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872935.pdf [firstpage_image] =>[orig_patent_app_number] => 12492879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492879
Memory cells with power switch circuit for improved low voltage operation Jun 25, 2009 Issued
Array ( [id] => 4625606 [patent_doc_number] => 08004912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Block redundancy implementation in hierarchical rams' [patent_app_type] => utility [patent_app_number] => 12/491864 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 44 [patent_no_of_words] => 18166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004912.pdf [firstpage_image] =>[orig_patent_app_number] => 12491864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491864
Block redundancy implementation in hierarchical rams Jun 24, 2009 Issued
Array ( [id] => 7520033 [patent_doc_number] => 07974138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/491658 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 15326 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/974/07974138.pdf [firstpage_image] =>[orig_patent_app_number] => 12491658 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491658
Semiconductor memory device Jun 24, 2009 Issued
Array ( [id] => 6426180 [patent_doc_number] => 20100277975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/488632 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7188 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277975.pdf [firstpage_image] =>[orig_patent_app_number] => 12488632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488632
Semiconductor memory device Jun 21, 2009 Issued
Array ( [id] => 7969941 [patent_doc_number] => 07940545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Low power read scheme for read only memory (ROM)' [patent_app_type] => utility [patent_app_number] => 12/488624 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940545.pdf [firstpage_image] =>[orig_patent_app_number] => 12488624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488624
Low power read scheme for read only memory (ROM) Jun 21, 2009 Issued
Array ( [id] => 4601704 [patent_doc_number] => 07978543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same' [patent_app_type] => utility [patent_app_number] => 12/488920 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7904 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978543.pdf [firstpage_image] =>[orig_patent_app_number] => 12488920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488920
Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same Jun 21, 2009 Issued
Array ( [id] => 6520246 [patent_doc_number] => 20100220519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Sensing Characteristic Evaluating Apparatus for Semiconductor Device and Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/488916 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5198 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220519.pdf [firstpage_image] =>[orig_patent_app_number] => 12488916 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488916
Sensing characteristic evaluating apparatus for semiconductor device and method thereof Jun 21, 2009 Issued
Array ( [id] => 7797106 [patent_doc_number] => 08125816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 12/488450 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125816.pdf [firstpage_image] =>[orig_patent_app_number] => 12488450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488450
Semiconductor storage device Jun 18, 2009 Issued
Array ( [id] => 5402695 [patent_doc_number] => 20090238009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME' [patent_app_type] => utility [patent_app_number] => 12/480419 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3521 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20090238009.pdf [firstpage_image] =>[orig_patent_app_number] => 12480419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480419
System and method for reducing pin-count of memory devices, and memory device testers for same Jun 7, 2009 Issued
Array ( [id] => 5532110 [patent_doc_number] => 20090231898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same' [patent_app_type] => utility [patent_app_number] => 12/467331 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 14340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231898.pdf [firstpage_image] =>[orig_patent_app_number] => 12467331 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467331
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same May 17, 2009 Issued
Array ( [id] => 85828 [patent_doc_number] => 07742358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Power supply circuit and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/435069 [patent_app_country] => US [patent_app_date] => 2009-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7266 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742358.pdf [firstpage_image] =>[orig_patent_app_number] => 12435069 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/435069
Power supply circuit and semiconductor memory May 3, 2009 Issued
Array ( [id] => 7528806 [patent_doc_number] => 08045410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Memory cell array' [patent_app_type] => utility [patent_app_number] => 12/434084 [patent_app_country] => US [patent_app_date] => 2009-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6147 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045410.pdf [firstpage_image] =>[orig_patent_app_number] => 12434084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434084
Memory cell array Apr 30, 2009 Issued
Array ( [id] => 4559635 [patent_doc_number] => 07961500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/432796 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 6276 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961500.pdf [firstpage_image] =>[orig_patent_app_number] => 12432796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432796
Semiconductor device Apr 29, 2009 Issued
Array ( [id] => 6426322 [patent_doc_number] => 20100277990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'INTEGRATED CIRCUIT HAVING MEMORY REPAIR INFORMATION STORAGE AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/433330 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277990.pdf [firstpage_image] =>[orig_patent_app_number] => 12433330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/433330
Integrated circuit having memory repair information storage and method therefor Apr 29, 2009 Issued
Array ( [id] => 8008359 [patent_doc_number] => 08085588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Semiconductor device and control method thereof' [patent_app_type] => utility [patent_app_number] => 12/433084 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/085/08085588.pdf [firstpage_image] =>[orig_patent_app_number] => 12433084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/433084
Semiconductor device and control method thereof Apr 29, 2009 Issued
Array ( [id] => 6403548 [patent_doc_number] => 20100165717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'WRITE DRIVER CIRCUIT OF PRAM' [patent_app_type] => utility [patent_app_number] => 12/433068 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165717.pdf [firstpage_image] =>[orig_patent_app_number] => 12433068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/433068
Write driver circuit of PRAM Apr 29, 2009 Issued
Array ( [id] => 6426079 [patent_doc_number] => 20100277965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Memory System Having Multiple Vias at Junctions Between Traces' [patent_app_type] => utility [patent_app_number] => 12/432942 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277965.pdf [firstpage_image] =>[orig_patent_app_number] => 12432942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432942
Memory system having multiple vias at junctions between traces Apr 29, 2009 Issued
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