
Bernarr E. Gregory
Examiner (ID: 16577)
| Most Active Art Unit | 3648 |
| Art Unit(s) | 3642, 3646, 2202, 3662, 3648, 2766 |
| Total Applications | 4684 |
| Issued Applications | 4115 |
| Pending Applications | 277 |
| Abandoned Applications | 314 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5463235
[patent_doc_number] => 20090323435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/341886
[patent_app_country] => US
[patent_app_date] => 2008-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0323/20090323435.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/341886 | Time reduction of address setup/hold time for semiconductor memory | Dec 21, 2008 | Issued |
Array
(
[id] => 4577033
[patent_doc_number] => 07848130
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[patent_kind] => B1
[patent_issue_date] => 2010-12-07
[patent_title] => 'Method and apparatus for improving SRAM write operations'
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[patent_app_date] => 2008-12-19
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Array
(
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[patent_doc_number] => 08000129
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[patent_issue_date] => 2011-08-16
[patent_title] => 'Field-emitter-based memory array with phase-change storage devices'
[patent_app_type] => utility
[patent_app_number] => 12/339696
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Array
(
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[patent_doc_number] => 08059447
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[patent_issue_date] => 2011-11-15
[patent_title] => 'Capacitive discharge method for writing to non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 12/339338
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/339338 | Capacitive discharge method for writing to non-volatile memory | Dec 18, 2008 | Issued |
Array
(
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[patent_title] => 'Self-refresh based power saving circuit and method'
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Array
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[patent_title] => 'Voltage shifting word-line driver and method therefor'
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Array
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[patent_title] => 'Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor'
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[patent_app_number] => 12/339722
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/339722 | Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor | Dec 18, 2008 | Issued |
Array
(
[id] => 4435832
[patent_doc_number] => 07969759
[patent_country] => US
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[patent_issue_date] => 2011-06-28
[patent_title] => 'Method and apparatus for improving SRAM write operations'
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Array
(
[id] => 55587
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[patent_issue_date] => 2010-08-10
[patent_title] => 'Systems and methods for reading data from a memory array'
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Array
(
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[patent_title] => 'Memory including a performance test circuit'
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Array
(
[id] => 7970009
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Array
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[id] => 4571248
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Array
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Array
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Array
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Array
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