Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5463235 [patent_doc_number] => 20090323435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/341886 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20090323435.pdf [firstpage_image] =>[orig_patent_app_number] => 12341886 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341886
Time reduction of address setup/hold time for semiconductor memory Dec 21, 2008 Issued
Array ( [id] => 4577033 [patent_doc_number] => 07848130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Method and apparatus for improving SRAM write operations' [patent_app_type] => utility [patent_app_number] => 12/339584 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4799 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/848/07848130.pdf [firstpage_image] =>[orig_patent_app_number] => 12339584 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339584
Method and apparatus for improving SRAM write operations Dec 18, 2008 Issued
Array ( [id] => 4620405 [patent_doc_number] => 08000129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Field-emitter-based memory array with phase-change storage devices' [patent_app_type] => utility [patent_app_number] => 12/339696 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8986 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/000/08000129.pdf [firstpage_image] =>[orig_patent_app_number] => 12339696 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339696
Field-emitter-based memory array with phase-change storage devices Dec 18, 2008 Issued
Array ( [id] => 7541599 [patent_doc_number] => 08059447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Capacitive discharge method for writing to non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/339338 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 13965 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/059/08059447.pdf [firstpage_image] =>[orig_patent_app_number] => 12339338 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339338
Capacitive discharge method for writing to non-volatile memory Dec 18, 2008 Issued
Array ( [id] => 4605597 [patent_doc_number] => 07986580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Self-refresh based power saving circuit and method' [patent_app_type] => utility [patent_app_number] => 12/339768 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3701 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986580.pdf [firstpage_image] =>[orig_patent_app_number] => 12339768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339768
Self-refresh based power saving circuit and method Dec 18, 2008 Issued
Array ( [id] => 7970011 [patent_doc_number] => 07940580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Voltage shifting word-line driver and method therefor' [patent_app_type] => utility [patent_app_number] => 12/339952 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3103 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940580.pdf [firstpage_image] =>[orig_patent_app_number] => 12339952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339952
Voltage shifting word-line driver and method therefor Dec 18, 2008 Issued
Array ( [id] => 5513342 [patent_doc_number] => 20090213648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Integrated Circuit Comprising a Thyristor and Method of Controlling a Memory Cell Comprising a Thyristor' [patent_app_type] => utility [patent_app_number] => 12/339722 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4808 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213648.pdf [firstpage_image] =>[orig_patent_app_number] => 12339722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339722
Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor Dec 18, 2008 Issued
Array ( [id] => 4435832 [patent_doc_number] => 07969759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method and apparatus for improving SRAM write operations' [patent_app_type] => utility [patent_app_number] => 12/339618 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4794 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969759.pdf [firstpage_image] =>[orig_patent_app_number] => 12339618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339618
Method and apparatus for improving SRAM write operations Dec 18, 2008 Issued
Array ( [id] => 55587 [patent_doc_number] => 07773431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Systems and methods for reading data from a memory array' [patent_app_type] => utility [patent_app_number] => 12/337946 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 12237 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773431.pdf [firstpage_image] =>[orig_patent_app_number] => 12337946 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/337946
Systems and methods for reading data from a memory array Dec 17, 2008 Issued
Array ( [id] => 74036 [patent_doc_number] => 07755960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Memory including a performance test circuit' [patent_app_type] => utility [patent_app_number] => 12/333426 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755960.pdf [firstpage_image] =>[orig_patent_app_number] => 12333426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/333426
Memory including a performance test circuit Dec 11, 2008 Issued
Array ( [id] => 7970009 [patent_doc_number] => 07940579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/332688 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940579.pdf [firstpage_image] =>[orig_patent_app_number] => 12332688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332688
Semiconductor integrated circuit device Dec 10, 2008 Issued
Array ( [id] => 4571248 [patent_doc_number] => 07839690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Adaptive erase and soft programming for memory' [patent_app_type] => utility [patent_app_number] => 12/332646 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 12249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/839/07839690.pdf [firstpage_image] =>[orig_patent_app_number] => 12332646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332646
Adaptive erase and soft programming for memory Dec 10, 2008 Issued
Array ( [id] => 4515315 [patent_doc_number] => 07916561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'DLL circuit, imaging device, and memory device' [patent_app_type] => utility [patent_app_number] => 12/332844 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8654 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/916/07916561.pdf [firstpage_image] =>[orig_patent_app_number] => 12332844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332844
DLL circuit, imaging device, and memory device Dec 10, 2008 Issued
Array ( [id] => 4560017 [patent_doc_number] => 07961541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Memory device with self-refresh operations' [patent_app_type] => utility [patent_app_number] => 12/332740 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7242 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961541.pdf [firstpage_image] =>[orig_patent_app_number] => 12332740 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332740
Memory device with self-refresh operations Dec 10, 2008 Issued
Array ( [id] => 5526013 [patent_doc_number] => 20090196090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Nanoscale Shift Register And Signal Demultiplexing Using Microscale/Nanoscale Shift Registers' [patent_app_type] => utility [patent_app_number] => 12/331642 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 8662 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196090.pdf [firstpage_image] =>[orig_patent_app_number] => 12331642 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331642
Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers Dec 9, 2008 Issued
Array ( [id] => 8318457 [patent_doc_number] => 08233243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Head suspension assembly interconnect for a data storage device' [patent_app_type] => utility [patent_app_number] => 12/331606 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 5311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12331606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/331606
Head suspension assembly interconnect for a data storage device Dec 9, 2008 Issued
Array ( [id] => 7803908 [patent_doc_number] => 08132192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Optical disk apparatus' [patent_app_type] => utility [patent_app_number] => 12/330120 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1738 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132192.pdf [firstpage_image] =>[orig_patent_app_number] => 12330120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/330120
Optical disk apparatus Dec 7, 2008 Issued
Array ( [id] => 5574034 [patent_doc_number] => 20090141395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'MOUNTING METHOD FOR STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/325204 [patent_app_country] => US [patent_app_date] => 2008-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4196 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141395.pdf [firstpage_image] =>[orig_patent_app_number] => 12325204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/325204
MOUNTING METHOD FOR STORAGE MEDIUM Nov 29, 2008 Abandoned
Array ( [id] => 4475322 [patent_doc_number] => RE042202 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof' [patent_app_type] => reissue [patent_app_number] => 12/315173 [patent_app_country] => US [patent_app_date] => 2008-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8943 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042202.pdf [firstpage_image] =>[orig_patent_app_number] => 12315173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/315173
Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof Nov 27, 2008 Issued
Array ( [id] => 7546607 [patent_doc_number] => 08054584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Top bond pad bias and variation control' [patent_app_type] => utility [patent_app_number] => 12/324503 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4716 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/054/08054584.pdf [firstpage_image] =>[orig_patent_app_number] => 12324503 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324503
Top bond pad bias and variation control Nov 25, 2008 Issued
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