Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4540933 [patent_doc_number] => 07872909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Memory device and memory data read method' [patent_app_type] => utility [patent_app_number] => 12/219665 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9975 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872909.pdf [firstpage_image] =>[orig_patent_app_number] => 12219665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219665
Memory device and memory data read method Jul 24, 2008 Issued
Array ( [id] => 5359521 [patent_doc_number] => 20090034315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Memory core and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 12/220422 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034315.pdf [firstpage_image] =>[orig_patent_app_number] => 12220422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/220422
Memory core and semiconductor memory device having the same Jul 23, 2008 Issued
Array ( [id] => 4544511 [patent_doc_number] => 07889574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Semiconductor memory device employing clamp for preventing latch up' [patent_app_type] => utility [patent_app_number] => 12/219572 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889574.pdf [firstpage_image] =>[orig_patent_app_number] => 12219572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219572
Semiconductor memory device employing clamp for preventing latch up Jul 23, 2008 Issued
Array ( [id] => 6429436 [patent_doc_number] => 20100187218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Method for heating at least one component of an SCR system using resistive heating elements' [patent_app_type] => utility [patent_app_number] => 12/670275 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4383 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187218.pdf [firstpage_image] =>[orig_patent_app_number] => 12670275 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/670275
Method for heating at least one component of an SCR system using resistive heating elements Jul 23, 2008 Issued
Array ( [id] => 4445197 [patent_doc_number] => 07929372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Decoder, memory system, and physical position converting method thereof' [patent_app_type] => utility [patent_app_number] => 12/219600 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9726 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/929/07929372.pdf [firstpage_image] =>[orig_patent_app_number] => 12219600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219600
Decoder, memory system, and physical position converting method thereof Jul 23, 2008 Issued
Array ( [id] => 4522074 [patent_doc_number] => 07911819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules' [patent_app_type] => utility [patent_app_number] => 12/179423 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3850 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911819.pdf [firstpage_image] =>[orig_patent_app_number] => 12179423 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179423
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules Jul 23, 2008 Issued
Array ( [id] => 5359552 [patent_doc_number] => 20090034346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Memory read control circuit' [patent_app_type] => utility [patent_app_number] => 12/219521 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3349 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034346.pdf [firstpage_image] =>[orig_patent_app_number] => 12219521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219521
Memory read control circuit Jul 22, 2008 Issued
Array ( [id] => 4438840 [patent_doc_number] => 07898881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Semiconductor memory device and data sensing method thereof' [patent_app_type] => utility [patent_app_number] => 12/219494 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898881.pdf [firstpage_image] =>[orig_patent_app_number] => 12219494 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219494
Semiconductor memory device and data sensing method thereof Jul 22, 2008 Issued
Array ( [id] => 104523 [patent_doc_number] => 07729150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'High-speed and low-power differential non-volatile content addressable memory cell and array' [patent_app_type] => utility [patent_app_number] => 12/176281 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5873 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729150.pdf [firstpage_image] =>[orig_patent_app_number] => 12176281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176281
High-speed and low-power differential non-volatile content addressable memory cell and array Jul 17, 2008 Issued
Array ( [id] => 261047 [patent_doc_number] => 07573778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/173124 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8068 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573778.pdf [firstpage_image] =>[orig_patent_app_number] => 12173124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173124
Semiconductor memory device Jul 14, 2008 Issued
Array ( [id] => 229848 [patent_doc_number] => 07602665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/169253 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 14327 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602665.pdf [firstpage_image] =>[orig_patent_app_number] => 12169253 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169253
Semiconductor integrated circuit device Jul 7, 2008 Issued
Array ( [id] => 5295159 [patent_doc_number] => 20090010085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND REDUNDANCY METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/165720 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010085.pdf [firstpage_image] =>[orig_patent_app_number] => 12165720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165720
Semiconductor integrated circuit device and redundancy method thereof Jun 30, 2008 Issued
Array ( [id] => 6605864 [patent_doc_number] => 20100002503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation' [patent_app_type] => utility [patent_app_number] => 12/166112 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16407 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002503.pdf [firstpage_image] =>[orig_patent_app_number] => 12166112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166112
Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation Jun 30, 2008 Issued
Array ( [id] => 44972 [patent_doc_number] => 07782655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Ultra-low power hybrid sub-threshold circuits' [patent_app_type] => utility [patent_app_number] => 12/165658 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4069 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782655.pdf [firstpage_image] =>[orig_patent_app_number] => 12165658 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165658
Ultra-low power hybrid sub-threshold circuits Jun 30, 2008 Issued
Array ( [id] => 4858102 [patent_doc_number] => 20080266952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'MEMORY ARRAY ARCHITECTURE FOR A MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY ARRAY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/166246 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17274 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266952.pdf [firstpage_image] =>[orig_patent_app_number] => 12166246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166246
Memory array architecture for a memory device and method of operating the memory array architecture Jun 30, 2008 Issued
Array ( [id] => 4584376 [patent_doc_number] => 07826245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/164486 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7187 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826245.pdf [firstpage_image] =>[orig_patent_app_number] => 12164486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164486
Semiconductor memory Jun 29, 2008 Issued
Array ( [id] => 4661454 [patent_doc_number] => 20080252361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'ELECTRICAL FUSES WITH REDUNDANCY' [patent_app_type] => utility [patent_app_number] => 12/145879 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20080252361.pdf [firstpage_image] =>[orig_patent_app_number] => 12145879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145879
Electrical fuses with redundancy Jun 24, 2008 Issued
Array ( [id] => 115525 [patent_doc_number] => 07715221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Apparatus for implementing domino SRAM leakage current reduction' [patent_app_type] => utility [patent_app_number] => 12/143864 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3359 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715221.pdf [firstpage_image] =>[orig_patent_app_number] => 12143864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143864
Apparatus for implementing domino SRAM leakage current reduction Jun 22, 2008 Issued
Array ( [id] => 4445140 [patent_doc_number] => 07929332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Semiconductor memory device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/144032 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 17651 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/929/07929332.pdf [firstpage_image] =>[orig_patent_app_number] => 12144032 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144032
Semiconductor memory device and semiconductor device Jun 22, 2008 Issued
Array ( [id] => 5289276 [patent_doc_number] => 20090022006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'INTEGRATED LOGIC CIRCUIT AND METHOD FOR PRODUCING AN INTEGRATED LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/142910 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20090022006.pdf [firstpage_image] =>[orig_patent_app_number] => 12142910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142910
Integrated logic circuit and method for producing an integrated logic circuit Jun 19, 2008 Issued
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