Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4844574 [patent_doc_number] => 20080180982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Stacked 1T-nmemory cell structure' [patent_app_type] => utility [patent_app_number] => 12/010651 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4900 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20080180982.pdf [firstpage_image] =>[orig_patent_app_number] => 12010651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010651
Stacked memory cell structure and method of forming such a structure Jan 27, 2008 Issued
Array ( [id] => 4898058 [patent_doc_number] => 20080117671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES' [patent_app_type] => utility [patent_app_number] => 12/018915 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3809 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117671.pdf [firstpage_image] =>[orig_patent_app_number] => 12018915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018915
Memory devices using carbon nanotube (CNT) technologies Jan 23, 2008 Issued
Array ( [id] => 5341665 [patent_doc_number] => 20090180315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'System and Method of Selectively Applying Negative Voltage to Wordlines During Memory Device Read Operation' [patent_app_type] => utility [patent_app_number] => 11/972696 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5765 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20090180315.pdf [firstpage_image] =>[orig_patent_app_number] => 11972696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972696
System and method of selectively applying negative voltage to wordlines during memory device read operation Jan 10, 2008 Issued
Array ( [id] => 4680996 [patent_doc_number] => 20080247222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods' [patent_app_type] => utility [patent_app_number] => 11/972674 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20080247222.pdf [firstpage_image] =>[orig_patent_app_number] => 11972674 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972674
Spin transfer torque magnetoresistive random access memory and design methods Jan 10, 2008 Issued
Array ( [id] => 5341680 [patent_doc_number] => 20090180330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHODS OF USING' [patent_app_type] => utility [patent_app_number] => 11/972312 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20090180330.pdf [firstpage_image] =>[orig_patent_app_number] => 11972312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972312
Non-volatile memory device and methods of using Jan 9, 2008 Issued
Array ( [id] => 4806873 [patent_doc_number] => 20080170451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'METHOD AND CIRCUIT FOR SETTING TEST MODE OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/971606 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2836 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170451.pdf [firstpage_image] =>[orig_patent_app_number] => 11971606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971606
METHOD AND CIRCUIT FOR SETTING TEST MODE OF SEMICONDUCTOR MEMORY DEVICE Jan 8, 2008 Abandoned
Array ( [id] => 74012 [patent_doc_number] => 07755941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/971334 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 9615 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755941.pdf [firstpage_image] =>[orig_patent_app_number] => 11971334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971334
Nonvolatile semiconductor memory device Jan 8, 2008 Issued
Array ( [id] => 5579769 [patent_doc_number] => 20090175115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 11/971880 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3324 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175115.pdf [firstpage_image] =>[orig_patent_app_number] => 11971880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971880
MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING Jan 8, 2008 Abandoned
Array ( [id] => 4544594 [patent_doc_number] => 07889588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Circuit having gate oxide protection for low voltage fuse reads and high voltage fuse programming' [patent_app_type] => utility [patent_app_number] => 11/970782 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889588.pdf [firstpage_image] =>[orig_patent_app_number] => 11970782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970782
Circuit having gate oxide protection for low voltage fuse reads and high voltage fuse programming Jan 7, 2008 Issued
Array ( [id] => 4581589 [patent_doc_number] => 07859885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Phase changing memory device' [patent_app_type] => utility [patent_app_number] => 11/970154 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 40 [patent_no_of_words] => 14424 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859885.pdf [firstpage_image] =>[orig_patent_app_number] => 11970154 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970154
Phase changing memory device Jan 6, 2008 Issued
Array ( [id] => 187107 [patent_doc_number] => 07646643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-12 [patent_title] => 'Process charging monitor for nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/970212 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3490 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646643.pdf [firstpage_image] =>[orig_patent_app_number] => 11970212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970212
Process charging monitor for nonvolatile memory Jan 6, 2008 Issued
Array ( [id] => 4926204 [patent_doc_number] => 20080165567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/969972 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5800 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20080165567.pdf [firstpage_image] =>[orig_patent_app_number] => 11969972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969972
Semiconductor memory device Jan 6, 2008 Issued
Array ( [id] => 192049 [patent_doc_number] => 07643368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Power control circuit for semiconductor IC' [patent_app_type] => utility [patent_app_number] => 11/969968 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3781 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/643/07643368.pdf [firstpage_image] =>[orig_patent_app_number] => 11969968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969968
Power control circuit for semiconductor IC Jan 6, 2008 Issued
Array ( [id] => 5574209 [patent_doc_number] => 20090141570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM' [patent_app_type] => utility [patent_app_number] => 11/970188 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3734 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141570.pdf [firstpage_image] =>[orig_patent_app_number] => 11970188 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970188
Controlling global bit line pre-charge time for high speed eDRAM Jan 6, 2008 Issued
Array ( [id] => 7592300 [patent_doc_number] => 07652905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Flash memory array architecture' [patent_app_type] => utility [patent_app_number] => 11/969812 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652905.pdf [firstpage_image] =>[orig_patent_app_number] => 11969812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969812
Flash memory array architecture Jan 3, 2008 Issued
Array ( [id] => 218136 [patent_doc_number] => 07613049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Method and system for a serial peripheral interface' [patent_app_type] => utility [patent_app_number] => 11/969856 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 13159 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613049.pdf [firstpage_image] =>[orig_patent_app_number] => 11969856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969856
Method and system for a serial peripheral interface Jan 3, 2008 Issued
Array ( [id] => 5579721 [patent_doc_number] => 20090175067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'SRAM EMPLOYING A READ-ENABLING CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 11/969636 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5520 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175067.pdf [firstpage_image] =>[orig_patent_app_number] => 11969636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969636
SRAM employing a read-enabling capacitance Jan 3, 2008 Issued
Array ( [id] => 244271 [patent_doc_number] => 07590010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Data output circuit in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/006682 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590010.pdf [firstpage_image] =>[orig_patent_app_number] => 12006682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006682
Data output circuit in semiconductor memory device Jan 3, 2008 Issued
Array ( [id] => 4926196 [patent_doc_number] => 20080165559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Data line layout and line driving method in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/006502 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4616 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20080165559.pdf [firstpage_image] =>[orig_patent_app_number] => 12006502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006502
Data line layout and line driving method in semiconductor memory device Jan 2, 2008 Issued
Array ( [id] => 4885376 [patent_doc_number] => 20080259708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 11/968492 [patent_app_country] => US [patent_app_date] => 2008-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4915 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20080259708.pdf [firstpage_image] =>[orig_patent_app_number] => 11968492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968492
Memory controller Jan 1, 2008 Issued
Menu