Search

Bernarr E. Gregory

Examiner (ID: 11710, Phone: (571)272-6972 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
2202, 3646, 3648, 3642, 2766, 3662
Total Applications
4661
Issued Applications
4105
Pending Applications
272
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4369154 [patent_doc_number] => 06287949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Multi-chip semiconductor chip module' [patent_app_type] => 1 [patent_app_number] => 9/145027 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 47 [patent_no_of_words] => 7090 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287949.pdf [firstpage_image] =>[orig_patent_app_number] => 145027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145027
Multi-chip semiconductor chip module Aug 31, 1998 Issued
Array ( [id] => 4395460 [patent_doc_number] => 06297154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for semiconductor device fabrication having copper interconnects' [patent_app_type] => 1 [patent_app_number] => 9/143037 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3204 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297154.pdf [firstpage_image] =>[orig_patent_app_number] => 143037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143037
Process for semiconductor device fabrication having copper interconnects Aug 27, 1998 Issued
Array ( [id] => 1561204 [patent_doc_number] => 06362092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Planarization method on a damascene structure' [patent_app_type] => B1 [patent_app_number] => 09/143267 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1621 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362092.pdf [firstpage_image] =>[orig_patent_app_number] => 09143267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143267
Planarization method on a damascene structure Aug 27, 1998 Issued
Array ( [id] => 7640291 [patent_doc_number] => 06395623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions' [patent_app_type] => B1 [patent_app_number] => 09/141777 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3308 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395623.pdf [firstpage_image] =>[orig_patent_app_number] => 09141777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141777
Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions Aug 26, 1998 Issued
Array ( [id] => 4358456 [patent_doc_number] => 06255186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom' [patent_app_type] => 1 [patent_app_number] => 9/137780 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2776 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255186.pdf [firstpage_image] =>[orig_patent_app_number] => 137780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137780
Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom Aug 19, 1998 Issued
Array ( [id] => 4408798 [patent_doc_number] => 06300241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Silicon interconnect passivation and metallization process optimized to maximize reflectance' [patent_app_type] => 1 [patent_app_number] => 9/136627 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 58 [patent_no_of_words] => 8602 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300241.pdf [firstpage_image] =>[orig_patent_app_number] => 136627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136627
Silicon interconnect passivation and metallization process optimized to maximize reflectance Aug 18, 1998 Issued
Array ( [id] => 4154802 [patent_doc_number] => 06103616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method to manufacture dual damascene structures by utilizing short resist spacers' [patent_app_type] => 1 [patent_app_number] => 9/136867 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103616.pdf [firstpage_image] =>[orig_patent_app_number] => 136867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136867
Method to manufacture dual damascene structures by utilizing short resist spacers Aug 18, 1998 Issued
Array ( [id] => 1341737 [patent_doc_number] => 06586345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method of manufacturing a semiconductor device wiring layer having an oxide layer between the polysilicon and silicide layers' [patent_app_type] => B1 [patent_app_number] => 09/133404 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 3155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586345.pdf [firstpage_image] =>[orig_patent_app_number] => 09133404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133404
Method of manufacturing a semiconductor device wiring layer having an oxide layer between the polysilicon and silicide layers Aug 12, 1998 Issued
Array ( [id] => 4381696 [patent_doc_number] => 06294462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Manufacturing method of interconnection layer for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/129000 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2861 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294462.pdf [firstpage_image] =>[orig_patent_app_number] => 129000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129000
Manufacturing method of interconnection layer for semiconductor device Aug 3, 1998 Issued
Array ( [id] => 4084354 [patent_doc_number] => 06162717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of manufacturing MOS gate utilizing a nitridation reaction' [patent_app_type] => 1 [patent_app_number] => 9/128187 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2140 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162717.pdf [firstpage_image] =>[orig_patent_app_number] => 128187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128187
Method of manufacturing MOS gate utilizing a nitridation reaction Aug 2, 1998 Issued
Array ( [id] => 1585489 [patent_doc_number] => 06358810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes' [patent_app_type] => B1 [patent_app_number] => 09/123690 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5439 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358810.pdf [firstpage_image] =>[orig_patent_app_number] => 09123690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123690
Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes Jul 27, 1998 Issued
Array ( [id] => 1442041 [patent_doc_number] => 06335569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Soft metal conductor and method of making' [patent_app_type] => B1 [patent_app_number] => 09/112885 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6376 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335569.pdf [firstpage_image] =>[orig_patent_app_number] => 09112885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112885
Soft metal conductor and method of making Jul 8, 1998 Issued
Array ( [id] => 4359060 [patent_doc_number] => 06169012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Chemical mechanical polishing for forming a shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/111007 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2104 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169012.pdf [firstpage_image] =>[orig_patent_app_number] => 111007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111007
Chemical mechanical polishing for forming a shallow trench isolation structure Jul 6, 1998 Issued
Array ( [id] => 4356648 [patent_doc_number] => 06190934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Liquid crystal display device and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/109977 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 3837 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190934.pdf [firstpage_image] =>[orig_patent_app_number] => 109977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109977
Liquid crystal display device and a method for manufacturing the same Jul 1, 1998 Issued
Array ( [id] => 1523809 [patent_doc_number] => 06352940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Semiconductor passivation deposition process for interfacial adhesion' [patent_app_type] => B1 [patent_app_number] => 09/105590 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6075 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352940.pdf [firstpage_image] =>[orig_patent_app_number] => 09105590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105590
Semiconductor passivation deposition process for interfacial adhesion Jun 25, 1998 Issued
Array ( [id] => 4336088 [patent_doc_number] => 06333215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/098470 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6433 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333215.pdf [firstpage_image] =>[orig_patent_app_number] => 098470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098470
Method for manufacturing a semiconductor device Jun 16, 1998 Issued
Array ( [id] => 4420861 [patent_doc_number] => 06225236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for reforming undercoating surface and method for production of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/095750 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 7598 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225236.pdf [firstpage_image] =>[orig_patent_app_number] => 095750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095750
Method for reforming undercoating surface and method for production of semiconductor device Jun 10, 1998 Issued
Array ( [id] => 1453657 [patent_doc_number] => 06461970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby' [patent_app_type] => B1 [patent_app_number] => 09/095477 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4301 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461970.pdf [firstpage_image] =>[orig_patent_app_number] => 09095477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095477
Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby Jun 9, 1998 Issued
09/091070 METHOD FOR PRODUCING A NEURON MOS TRANSISTOR ON THE BASIS OF A CMOS PROCESS Jun 8, 1998 Abandoned
Array ( [id] => 4414391 [patent_doc_number] => 06229199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Packaged semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/092117 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3467 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229199.pdf [firstpage_image] =>[orig_patent_app_number] => 092117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092117
Packaged semiconductor device Jun 4, 1998 Issued
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