Search

Bernarr E. Gregory

Examiner (ID: 16577)

Most Active Art Unit
3648
Art Unit(s)
3642, 3646, 2202, 3662, 3648, 2766
Total Applications
4684
Issued Applications
4115
Pending Applications
277
Abandoned Applications
314

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5681910 [patent_doc_number] => 20060198180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES' [patent_app_type] => utility [patent_app_number] => 11/419166 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9197 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20060198180.pdf [firstpage_image] =>[orig_patent_app_number] => 11419166 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/419166
Distributed write data drivers for burst access memories May 17, 2006 Issued
Array ( [id] => 879171 [patent_doc_number] => 07359241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'In-service reconfigurable DRAM and flash memory device' [patent_app_type] => utility [patent_app_number] => 11/435621 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3115 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359241.pdf [firstpage_image] =>[orig_patent_app_number] => 11435621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435621
In-service reconfigurable DRAM and flash memory device May 16, 2006 Issued
Array ( [id] => 5757360 [patent_doc_number] => 20060208305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'In-service reconfigurable DRAM and flash memory device' [patent_app_type] => utility [patent_app_number] => 11/435620 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20060208305.pdf [firstpage_image] =>[orig_patent_app_number] => 11435620 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435620
In-service reconfigurable DRAM and flash memory device May 16, 2006 Issued
Array ( [id] => 455588 [patent_doc_number] => 07248516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Data compression read mode for memory testing' [patent_app_type] => utility [patent_app_number] => 11/430339 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248516.pdf [firstpage_image] =>[orig_patent_app_number] => 11430339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430339
Data compression read mode for memory testing May 8, 2006 Issued
Array ( [id] => 416711 [patent_doc_number] => 07280420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Data compression read mode for memory testing' [patent_app_type] => utility [patent_app_number] => 11/430549 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6884 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/280/07280420.pdf [firstpage_image] =>[orig_patent_app_number] => 11430549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430549
Data compression read mode for memory testing May 8, 2006 Issued
Array ( [id] => 5854525 [patent_doc_number] => 20060226458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Magnetic memory having synthetic antiferromagnetic pinned layer' [patent_app_type] => utility [patent_app_number] => 11/430138 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3039 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226458.pdf [firstpage_image] =>[orig_patent_app_number] => 11430138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430138
Magnetic memory having synthetic antiferromagnetic pinned layer May 8, 2006 Issued
Array ( [id] => 5698786 [patent_doc_number] => 20060215470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Data compression read mode for memory testing' [patent_app_type] => utility [patent_app_number] => 11/430550 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6878 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20060215470.pdf [firstpage_image] =>[orig_patent_app_number] => 11430550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430550
Data compression read mode for memory testing May 8, 2006 Issued
Array ( [id] => 891426 [patent_doc_number] => 07349277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Method and system for reducing the peak current in refreshing dynamic random access memory devices' [patent_app_type] => utility [patent_app_number] => 11/431371 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6431 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/349/07349277.pdf [firstpage_image] =>[orig_patent_app_number] => 11431371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/431371
Method and system for reducing the peak current in refreshing dynamic random access memory devices May 8, 2006 Issued
Array ( [id] => 5752551 [patent_doc_number] => 20060221700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Charge packet metering for coarse/fine programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/429769 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14138 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221700.pdf [firstpage_image] =>[orig_patent_app_number] => 11429769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429769
Charge packet metering for coarse/fine programming of non-volatile memory May 7, 2006 Issued
Array ( [id] => 593252 [patent_doc_number] => 07447075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Charge packet metering for coarse/fine programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/429770 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 14135 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447075.pdf [firstpage_image] =>[orig_patent_app_number] => 11429770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429770
Charge packet metering for coarse/fine programming of non-volatile memory May 7, 2006 Issued
Array ( [id] => 5856375 [patent_doc_number] => 20060227600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 11/381578 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10523 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20060227600.pdf [firstpage_image] =>[orig_patent_app_number] => 11381578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381578
Non-volatile memory device May 3, 2006 Issued
Array ( [id] => 377916 [patent_doc_number] => 07313020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Multi-level nonvolatile semiconductor memory device and method for reading the same' [patent_app_type] => utility [patent_app_number] => 11/416064 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8421 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313020.pdf [firstpage_image] =>[orig_patent_app_number] => 11416064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416064
Multi-level nonvolatile semiconductor memory device and method for reading the same May 2, 2006 Issued
Array ( [id] => 5641534 [patent_doc_number] => 20060279989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Method of controlling copy-back operation of flash memory device including multi-level cells' [patent_app_type] => utility [patent_app_number] => 11/416070 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9205 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20060279989.pdf [firstpage_image] =>[orig_patent_app_number] => 11416070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416070
Method of controlling copy-back operation of flash memory device including multi-level cells May 2, 2006 Issued
Array ( [id] => 895106 [patent_doc_number] => 07345922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Position based erase verification levels in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/416582 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2224 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345922.pdf [firstpage_image] =>[orig_patent_app_number] => 11416582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416582
Position based erase verification levels in a flash memory device May 2, 2006 Issued
Array ( [id] => 5257913 [patent_doc_number] => 20070211545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/416122 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20070211545.pdf [firstpage_image] =>[orig_patent_app_number] => 11416122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416122
Semiconductor memory device May 2, 2006 Issued
Array ( [id] => 842133 [patent_doc_number] => 07391649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Page buffer and non-volatile memory device including the same' [patent_app_type] => utility [patent_app_number] => 11/416320 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 7203 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391649.pdf [firstpage_image] =>[orig_patent_app_number] => 11416320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416320
Page buffer and non-volatile memory device including the same May 2, 2006 Issued
Array ( [id] => 5607105 [patent_doc_number] => 20060268621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Method for programming a reference cell' [patent_app_type] => utility [patent_app_number] => 11/413962 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7690 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268621.pdf [firstpage_image] =>[orig_patent_app_number] => 11413962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413962
Method for programming a reference cell Apr 26, 2006 Issued
Array ( [id] => 5671382 [patent_doc_number] => 20060176736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element' [patent_app_type] => utility [patent_app_number] => 11/379004 [patent_app_country] => US [patent_app_date] => 2006-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176736.pdf [firstpage_image] =>[orig_patent_app_number] => 11379004 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379004
Flash memory cell arrays having dual control gates per memory cell charge storage element Apr 16, 2006 Issued
Array ( [id] => 5618181 [patent_doc_number] => 20060187714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element' [patent_app_type] => utility [patent_app_number] => 11/379019 [patent_app_country] => US [patent_app_date] => 2006-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10521 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187714.pdf [firstpage_image] =>[orig_patent_app_number] => 11379019 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379019
Flash memory cell arrays having dual control gates per memory cell charge storage element Apr 16, 2006 Issued
Array ( [id] => 844909 [patent_doc_number] => 07388788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Reference current generating circuit of nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/401278 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8379 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/388/07388788.pdf [firstpage_image] =>[orig_patent_app_number] => 11401278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401278
Reference current generating circuit of nonvolatile semiconductor memory device Apr 10, 2006 Issued
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