Search

Beth A. Stephan

Examiner (ID: 6858, Phone: (571)272-1851 , Office: P/3633 )

Most Active Art Unit
3633
Art Unit(s)
3637, 3633, 3504, 2899, 3621, 3635
Total Applications
2113
Issued Applications
1774
Pending Applications
82
Abandoned Applications
286

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19764952 [patent_doc_number] => 12223243 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-11 [patent_title] => Prediction method for water quality biotoxicity based on artificial intelligence neural network [patent_app_type] => utility [patent_app_number] => 18/820276 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4984 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1626 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820276
Prediction method for water quality biotoxicity based on artificial intelligence neural network Aug 29, 2024 Issued
Array ( [id] => 19802132 [patent_doc_number] => 20250068057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => CONCURRENT MASK OPTIMIZATION FOR MULTIPLE LAYERS [patent_app_type] => utility [patent_app_number] => 18/814439 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814439
CONCURRENT MASK OPTIMIZATION FOR MULTIPLE LAYERS Aug 22, 2024 Pending
Array ( [id] => 20079747 [patent_doc_number] => 12353816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Structure and method of rectangular cell in semiconductor device [patent_app_type] => utility [patent_app_number] => 18/741840 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741840
Structure and method of rectangular cell in semiconductor device Jun 12, 2024 Issued
Array ( [id] => 19574180 [patent_doc_number] => 20240378472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => ACTIVE STABILIZATION OF COHERENT CONTROLLERS USING NEARBY QUBITS [patent_app_type] => utility [patent_app_number] => 18/637172 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637172
Active stabilization of coherent controllers using nearby qubits Apr 15, 2024 Issued
Array ( [id] => 19925092 [patent_doc_number] => 12299376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Hard-to-fix (HTF) design rule check (DRC) violations prediction [patent_app_type] => utility [patent_app_number] => 18/437740 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 5681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437740 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437740
Hard-to-fix (HTF) design rule check (DRC) violations prediction Feb 8, 2024 Issued
Array ( [id] => 19191716 [patent_doc_number] => 20240170629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/430477 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430477
Display apparatus and method of manufacturing the same Jan 31, 2024 Issued
Array ( [id] => 19131491 [patent_doc_number] => 20240136844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => APPARATUS AND METHOD FOR CONTROLLING STEP CHARGING OF SECONDARY BATTERY [patent_app_type] => utility [patent_app_number] => 18/529990 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529990
Apparatus and method for controlling step charging of secondary battery Dec 4, 2023 Issued
Array ( [id] => 19053463 [patent_doc_number] => 20240095432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => DETERMINATION OF RECIPES FOR MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/385823 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/385823
DETERMINATION OF RECIPES FOR MANUFACTURING SEMICONDUCTOR DEVICES Oct 30, 2023 Pending
Array ( [id] => 19100098 [patent_doc_number] => 20240119326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => Multi-State Qubit Readout with Permutation Sequences [patent_app_type] => utility [patent_app_number] => 18/483758 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483758
Multi-state qubit readout with permutation sequences Oct 9, 2023 Issued
Array ( [id] => 19787584 [patent_doc_number] => 20250061263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => TEMPORAL CONTROL OF FAULT FUNCTIONAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 18/452447 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452447
TEMPORAL CONTROL OF FAULT FUNCTIONAL VERIFICATION Aug 17, 2023 Pending
Array ( [id] => 19250588 [patent_doc_number] => 20240201578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND METHOD OF MANUFACTURING MASK BY USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/449078 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449078
OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND METHOD OF MANUFACTURING MASK BY USING THE SAME Aug 13, 2023 Pending
Array ( [id] => 19334621 [patent_doc_number] => 20240249051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MEMORY DEVICE, ELECTRONIC DEVICE, AND OPERATING METHOD OF MEMORY DEVICE FOR VOTING VALID SIGNAL [patent_app_type] => utility [patent_app_number] => 18/449304 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449304 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449304
MEMORY DEVICE, ELECTRONIC DEVICE, AND OPERATING METHOD OF MEMORY DEVICE FOR VOTING VALID SIGNAL Aug 13, 2023 Pending
Array ( [id] => 19443361 [patent_doc_number] => 12093630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Method and computing device for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 18/360209 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6932 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360209
Method and computing device for manufacturing semiconductor device Jul 26, 2023 Issued
Array ( [id] => 19748279 [patent_doc_number] => 20250036844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/359128 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359128
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM Jul 25, 2023 Pending
Array ( [id] => 19747623 [patent_doc_number] => 20250036188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => POWER REDUCTION BY REMOVAL OF REDUNDANCY IN CLOCK PATHWAYS OF VLSI CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/357244 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357244
POWER REDUCTION BY REMOVAL OF REDUNDANCY IN CLOCK PATHWAYS OF VLSI CIRCUITS Jul 23, 2023 Pending
Array ( [id] => 19748278 [patent_doc_number] => 20250036843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => USING SIGNED DISTANCE FUNCTIONS TO EVALUATE FABRICABILITY OF PHOTONIC DEVICES DURING AN INVERSE DESIGN PROCESS [patent_app_type] => utility [patent_app_number] => 18/357846 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357846
USING SIGNED DISTANCE FUNCTIONS TO EVALUATE FABRICABILITY OF PHOTONIC DEVICES DURING AN INVERSE DESIGN PROCESS Jul 23, 2023 Pending
Array ( [id] => 19902691 [patent_doc_number] => 12279675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Article of footwear and charging system [patent_app_type] => utility [patent_app_number] => 18/218305 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9284 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218305
Article of footwear and charging system Jul 4, 2023 Issued
Array ( [id] => 19686776 [patent_doc_number] => 20250005321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MULTI-BRANCH NEURAL NETWORKS FOR DEFECT PREDICTIONS IN INTEGRATED CIRCUIT (IC) DESIGNS [patent_app_type] => utility [patent_app_number] => 18/344252 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344252
MULTI-BRANCH NEURAL NETWORKS FOR DEFECT PREDICTIONS IN INTEGRATED CIRCUIT (IC) DESIGNS Jun 28, 2023 Pending
Array ( [id] => 19251433 [patent_doc_number] => 20240202424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/335428 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335428 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335428
METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME Jun 14, 2023 Pending
Array ( [id] => 19905711 [patent_doc_number] => 12282718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Apparatus and method for generating a manufacturability analysis [patent_app_type] => utility [patent_app_number] => 18/208145 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12538 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208145
Apparatus and method for generating a manufacturability analysis Jun 8, 2023 Issued
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