Beth A. Stephan

Array ( [id] => 18211975 [patent_doc_number] => 20230058239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => TECHNIQUES FOR DETERMINING AND USING STATIC REGIONS IN AN INVERSE DESIGN PROCESS [patent_app_type] => utility [patent_app_number] => 18/048702 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18471677 [patent_doc_number] => 20230205963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => LAYOUT METHOD OF SEMICONDUCTOR CHIP, SEMICONDUCTOR CHIP MANUFACTURING METHOD AND COMPUTING DEVICE USING SAME [patent_app_type] => utility [patent_app_number] => 17/961710 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18306660 [patent_doc_number] => 20230110560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => UNIFIED FRAMEWORK AND METHOD FOR ACCURATE CONTEXT-AWARE TIMING MODELING [patent_app_type] => utility [patent_app_number] => 17/961415 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20716710 [patent_doc_number] => 12631955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Method of correcting an error of a layout of a pattern, method of manufacturing a photomask using the same, and method of forming a pattern using the same [patent_app_type] => utility [patent_app_number] => 17/938138 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 3327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069128 [patent_doc_number] => 20240103554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Systems and Methods for Dynamically Changing Regulator Voltage of a Scanning Device Having an Illumination System and an Imager [patent_app_type] => utility [patent_app_number] => 17/955424 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069835 [patent_doc_number] => 20240104261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => USING LINEAR MODELS TO ACCELERATE DESIGN AND FABRICATION OF PHYSICAL DEVICES [patent_app_type] => utility [patent_app_number] => 17/945916 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18281554 [patent_doc_number] => 20230097026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => QUANTUM COMPUTING SYSTEM BASED ON QUANTUM DOT QUBITS AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/903146 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20214755 [patent_doc_number] => 12411405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Optical proximity correction based on combining inverse lithography technology with pattern classification [patent_app_type] => utility [patent_app_number] => 17/823679 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4141 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19006299 [patent_doc_number] => 20240070370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CLOCK DOMAIN CROSSING VERIFICATION WITH SETUP ASSISTANCE [patent_app_type] => utility [patent_app_number] => 17/900508 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19100103 [patent_doc_number] => 20240119331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PHYSICAL LAYOUTS OF MAJORANA-BASED QUBITS FOR IMPLEMENTATIONS OF PENTAGONAL TILINGS [patent_app_type] => utility [patent_app_number] => 17/896258 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19002960 [patent_doc_number] => 20240067031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHODS AND SYSTEMS FOR SUSTAINABLE CHARGING OF AN ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 17/822402 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18006763 [patent_doc_number] => 20220365529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ON-BOARD CHARGING STATION FOR A REMOTE CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 17/873602 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20579598 [patent_doc_number] => 12571845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Method and apparatus for calculating relative state-of-charge of battery [patent_app_type] => utility [patent_app_number] => 17/871755 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2094 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18422005 [patent_doc_number] => 20230176469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/812005 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17962470 [patent_doc_number] => 20220343051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/860985 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20386079 [patent_doc_number] => 12485793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Control method, control device, and non-transitory computer readable storage medium [patent_app_type] => utility [patent_app_number] => 17/856714 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7958 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18143634 [patent_doc_number] => 20230017484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => AUTOMATED CIRCUIT DESIGN VALIDATION [patent_app_type] => utility [patent_app_number] => 17/854029 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18856078 [patent_doc_number] => 11853662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Machine-learning enhanced compiler [patent_app_type] => utility [patent_app_number] => 17/845421 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15292 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18067283 [patent_doc_number] => 20220398371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => MACHINE LEARNING BASED AUTOMATIC ROUTING METHOD AND APPARATUS FOR SEMICONDUCTOR EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/806702 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18981419 [patent_doc_number] => 11906584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Simulation method and system of verifying operation of semiconductor memory device of memory module at design level [patent_app_type] => utility [patent_app_number] => 17/838298 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 9565 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838298 [rel_patent_id] =>[rel_patent_doc_number] =>)