Betsy Lee Deppe

Array ( [id] => 3737176 [patent_doc_number] => 05652773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Digital phase-locked loop for data separation' [patent_app_type] => 1 [patent_app_number] => 8/594596 [patent_app_country] => US [patent_app_date] => 1996-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3571 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652773.pdf [firstpage_image] =>[orig_patent_app_number] => 594596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891433 [patent_doc_number] => 05825833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Digital and analog reception apparatus' [patent_app_type] => 1 [patent_app_number] => 8/594183 [patent_app_country] => US [patent_app_date] => 1996-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6038 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825833.pdf [firstpage_image] =>[orig_patent_app_number] => 594183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758448 [patent_doc_number] => 05802113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Clock signal recovery system for communication systems using quadrature amplitude modulation' [patent_app_type] => 1 [patent_app_number] => 8/592219 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3034 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802113.pdf [firstpage_image] =>[orig_patent_app_number] => 592219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758376 [patent_doc_number] => 05802108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Waveform correction apparatus' [patent_app_type] => 1 [patent_app_number] => 8/592534 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802108.pdf [firstpage_image] =>[orig_patent_app_number] => 592534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3806001 [patent_doc_number] => 05727037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits' [patent_app_type] => 1 [patent_app_number] => 8/592736 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7709 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727037.pdf [firstpage_image] =>[orig_patent_app_number] => 592736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3637680 [patent_doc_number] => 05621758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'PWM Communication system' [patent_app_type] => 1 [patent_app_number] => 8/591718 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8659 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621758.pdf [firstpage_image] =>[orig_patent_app_number] => 591718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3868853 [patent_doc_number] => 05768325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Time-adjustable delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/591129 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 2440 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768325.pdf [firstpage_image] =>[orig_patent_app_number] => 591129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884567 [patent_doc_number] => 05838736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method and apparatus for generating carriers for phase demodulation having at least two phase states, and a corresponding demodulation stage' [patent_app_type] => 1 [patent_app_number] => 8/585462 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6429 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838736.pdf [firstpage_image] =>[orig_patent_app_number] => 585462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3875294 [patent_doc_number] => 05796796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Pointer adjustment jitter cancellation processor utilizing phase hopping and phase leaking techniques' [patent_app_type] => 1 [patent_app_number] => 8/584196 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4479 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796796.pdf [firstpage_image] =>[orig_patent_app_number] => 584196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3952458 [patent_doc_number] => 05930307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and apparatus for acquiring peak and valley values of a signal received by a radio communication device' [patent_app_type] => 1 [patent_app_number] => 8/583918 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4349 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930307.pdf [firstpage_image] =>[orig_patent_app_number] => 583918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3990294 [patent_doc_number] => 05917872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Single chip device for decoding analog signals carrying digital data' [patent_app_type] => 1 [patent_app_number] => 8/583064 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2905 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917872.pdf [firstpage_image] =>[orig_patent_app_number] => 583064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3743233 [patent_doc_number] => 05694440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Data synchronizer lock detector and method of operation thereof' [patent_app_type] => 1 [patent_app_number] => 8/582840 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3871 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694440.pdf [firstpage_image] =>[orig_patent_app_number] => 582840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3995528 [patent_doc_number] => 05862192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Methods and apparatus for equalization and decoding of digital communications channels using antenna diversity' [patent_app_type] => 1 [patent_app_number] => 8/580218 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9413 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862192.pdf [firstpage_image] =>[orig_patent_app_number] => 580218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891423 [patent_doc_number] => 05825832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method and device for the reception of signals affected by inter-symbol interface' [patent_app_type] => 1 [patent_app_number] => 8/578032 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5970 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825832.pdf [firstpage_image] =>[orig_patent_app_number] => 578032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3832938 [patent_doc_number] => 05790608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Apparatus and method for synchronizing clock signals for digital links in a packet switching mode' [patent_app_type] => 1 [patent_app_number] => 8/574840 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6973 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790608.pdf [firstpage_image] =>[orig_patent_app_number] => 574840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3670754 [patent_doc_number] => 05648986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Receiver in digital radio communication device with selective equalization' [patent_app_type] => 1 [patent_app_number] => 8/564239 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648986.pdf [firstpage_image] =>[orig_patent_app_number] => 564239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3982102 [patent_doc_number] => 05887030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Data reproducing apparatus having equalization characteristics which can be controlled' [patent_app_type] => 1 [patent_app_number] => 8/574350 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 5500 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887030.pdf [firstpage_image] =>[orig_patent_app_number] => 574350 [rel_patent_id] =>[rel_patent_doc_number] =>)