Search

Bhavesh M. Mehta

Supervisory Patent Examiner (ID: 15292, Phone: (571)272-7453 , Office: P/2665 )

Most Active Art Unit
2721
Art Unit(s)
2621, 2624, 2606, 2714, 2616, 2611, 2625, 2656, 2721, 2665
Total Applications
656
Issued Applications
507
Pending Applications
40
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17174928 [patent_doc_number] => 20210328599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => POLAR CODING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/322529 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322529
Polar coding method and apparatus May 16, 2021 Issued
Array ( [id] => 19428879 [patent_doc_number] => 12088320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Electronic device for low density parity check decoding, and method therefor [patent_app_type] => utility [patent_app_number] => 17/925587 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 16 [patent_no_of_words] => 20161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17925587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/925587
Electronic device for low density parity check decoding, and method therefor May 13, 2021 Issued
Array ( [id] => 18072757 [patent_doc_number] => 11531591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Method and system utilizing quintuple parity to provide fault tolerance [patent_app_type] => utility [patent_app_number] => 17/306728 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306728
Method and system utilizing quintuple parity to provide fault tolerance May 2, 2021 Issued
Array ( [id] => 17276586 [patent_doc_number] => 20210382784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => PROCESSING DEVICE, NON-TRANSITORY STORAGE MEDIUM, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 17/246994 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246994
PROCESSING DEVICE, NON-TRANSITORY STORAGE MEDIUM, AND SYSTEM May 2, 2021 Abandoned
Array ( [id] => 18519843 [patent_doc_number] => 11709734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Error correction with syndrome computation in a memory device [patent_app_type] => utility [patent_app_number] => 17/246509 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246509
Error correction with syndrome computation in a memory device Apr 29, 2021 Issued
Array ( [id] => 18703306 [patent_doc_number] => 11789817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Error correction for internal read operations [patent_app_type] => utility [patent_app_number] => 17/240471 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 15548 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240471
Error correction for internal read operations Apr 25, 2021 Issued
Array ( [id] => 17026179 [patent_doc_number] => 20210250051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => EARLY DECODING TERMINATION FOR A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/240979 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240979
Early decoding termination for a memory sub-system Apr 25, 2021 Issued
Array ( [id] => 18001662 [patent_doc_number] => 11502780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Channel decoding method and apparatus in wireless communications [patent_app_type] => utility [patent_app_number] => 17/232769 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6189 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232769
Channel decoding method and apparatus in wireless communications Apr 15, 2021 Issued
Array ( [id] => 18154724 [patent_doc_number] => 11567702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Resolving detected access anomalies in a vast storage network [patent_app_type] => utility [patent_app_number] => 17/301470 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301470
Resolving detected access anomalies in a vast storage network Apr 4, 2021 Issued
Array ( [id] => 18330765 [patent_doc_number] => 11636007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Memory system and operating method thereof for flushing data in data cache with parity [patent_app_type] => utility [patent_app_number] => 17/301452 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301452
Memory system and operating method thereof for flushing data in data cache with parity Apr 1, 2021 Issued
Array ( [id] => 17691019 [patent_doc_number] => 20220198312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SHORT-DEPTH SYNDROME EXTRACTION CIRCUITS FOR CALDERBANK SHOR STEANE (CSS) STABILIZER CODES [patent_app_type] => utility [patent_app_number] => 17/219383 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219383
Short-depth syndrome extraction circuits for Calderbank Shor Steane (CSS) stabilizer codes Mar 30, 2021 Issued
Array ( [id] => 18519842 [patent_doc_number] => 11709733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Metadata-assisted encoding and decoding for a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/216574 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216574
Metadata-assisted encoding and decoding for a memory sub-system Mar 28, 2021 Issued
Array ( [id] => 18104257 [patent_doc_number] => 11544143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Increased data reliability [patent_app_type] => utility [patent_app_number] => 17/213734 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213734
Increased data reliability Mar 25, 2021 Issued
Array ( [id] => 18030708 [patent_doc_number] => 11513897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Error correction on length-compatible polar codes for memory systems [patent_app_type] => utility [patent_app_number] => 17/203745 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203745
Error correction on length-compatible polar codes for memory systems Mar 15, 2021 Issued
Array ( [id] => 18154853 [patent_doc_number] => 11567832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Using copied data in a distributed storage network [patent_app_type] => utility [patent_app_number] => 17/199745 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199745
Using copied data in a distributed storage network Mar 11, 2021 Issued
Array ( [id] => 17086356 [patent_doc_number] => 20210281363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => Multi-Resource-Unit Aggregation [patent_app_type] => utility [patent_app_number] => 17/194627 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194627
Multi-resource-unit aggregation Mar 7, 2021 Issued
Array ( [id] => 18053013 [patent_doc_number] => 11526398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Determining an error encoding function ratio based on path performance [patent_app_type] => utility [patent_app_number] => 17/249539 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249539
Determining an error encoding function ratio based on path performance Mar 3, 2021 Issued
Array ( [id] => 17817277 [patent_doc_number] => 11422889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Memory system and controller for storing map data of volatile memory into nonvolatile memory device during power off operation [patent_app_type] => utility [patent_app_number] => 17/192389 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192389
Memory system and controller for storing map data of volatile memory into nonvolatile memory device during power off operation Mar 3, 2021 Issued
Array ( [id] => 16918724 [patent_doc_number] => 20210191816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => STORING CRITICAL DATA AT A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/249399 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249399
Storing critical data at a memory system Feb 28, 2021 Issued
Array ( [id] => 17832659 [patent_doc_number] => 20220269963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => QUANTUM ERROR CORRECTION WITH REALISTIC MEASUREMENT DATA [patent_app_type] => utility [patent_app_number] => 17/179625 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179625
Quantum error correction with realistic measurement data Feb 18, 2021 Issued
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