Search

Bhisma Mehta

Supervisory Patent Examiner (ID: 1145, Phone: (571)272-3383 , Office: P/3763 )

Most Active Art Unit
3767
Art Unit(s)
3306, 3767, 3734, 3783, 3763
Total Applications
544
Issued Applications
260
Pending Applications
69
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3460213 [patent_doc_number] => 05386530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Address translation device capable of obtaining a real address from a virtual address in a shorter time' [patent_app_type] => 1 [patent_app_number] => 7/889908 [patent_app_country] => US [patent_app_date] => 1992-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9530 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 611 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386530.pdf [firstpage_image] =>[orig_patent_app_number] => 889908 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/889908
Address translation device capable of obtaining a real address from a virtual address in a shorter time May 28, 1992 Issued
07/887327 RESPONSE RESOLVER FOR ASSOCIATIVE MEMORIES AND PARALLEL PROCESSORS May 21, 1992 Abandoned
Array ( [id] => 3035197 [patent_doc_number] => 05327541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Global rotation of data in synchronous vector processor' [patent_app_type] => 1 [patent_app_number] => 7/887228 [patent_app_country] => US [patent_app_date] => 1992-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 71 [patent_no_of_words] => 29371 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327541.pdf [firstpage_image] =>[orig_patent_app_number] => 887228 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/887228
Global rotation of data in synchronous vector processor May 17, 1992 Issued
Array ( [id] => 3465191 [patent_doc_number] => 05379393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Cache memory system for vector processing' [patent_app_type] => 1 [patent_app_number] => 7/882857 [patent_app_country] => US [patent_app_date] => 1992-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 13310 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379393.pdf [firstpage_image] =>[orig_patent_app_number] => 882857 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/882857
Cache memory system for vector processing May 13, 1992 Issued
Array ( [id] => 3117699 [patent_doc_number] => 05448706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Address generator for multi-channel circular-buffer style processing' [patent_app_type] => 1 [patent_app_number] => 7/882645 [patent_app_country] => US [patent_app_date] => 1992-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17935 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448706.pdf [firstpage_image] =>[orig_patent_app_number] => 882645 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/882645
Address generator for multi-channel circular-buffer style processing May 12, 1992 Issued
Array ( [id] => 3460198 [patent_doc_number] => 05386529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Digital signal processor for use in sound quality treatment by filtering' [patent_app_type] => 1 [patent_app_number] => 7/877107 [patent_app_country] => US [patent_app_date] => 1992-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5678 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386529.pdf [firstpage_image] =>[orig_patent_app_number] => 877107 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/877107
Digital signal processor for use in sound quality treatment by filtering Apr 30, 1992 Issued
Array ( [id] => 3473332 [patent_doc_number] => 05392410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'History table for prediction of virtual address translation for cache access' [patent_app_type] => 1 [patent_app_number] => 7/876646 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8728 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392410.pdf [firstpage_image] =>[orig_patent_app_number] => 876646 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/876646
History table for prediction of virtual address translation for cache access Apr 29, 1992 Issued
Array ( [id] => 3502621 [patent_doc_number] => 05440707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle' [patent_app_type] => 1 [patent_app_number] => 7/875692 [patent_app_country] => US [patent_app_date] => 1992-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4739 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440707.pdf [firstpage_image] =>[orig_patent_app_number] => 875692 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/875692
Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle Apr 28, 1992 Issued
07/848968 MEMORY ACCESS SYSTEM Apr 23, 1992 Abandoned
Array ( [id] => 3047016 [patent_doc_number] => 05329627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method and apparatus for a translation lookaside buffer with built-in replacement scheme in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/870356 [patent_app_country] => US [patent_app_date] => 1992-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3136 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329627.pdf [firstpage_image] =>[orig_patent_app_number] => 870356 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/870356
Method and apparatus for a translation lookaside buffer with built-in replacement scheme in a computer system Apr 16, 1992 Issued
Array ( [id] => 3460118 [patent_doc_number] => 05386524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'System for accessing information in a data processing system' [patent_app_type] => 1 [patent_app_number] => 7/869668 [patent_app_country] => US [patent_app_date] => 1992-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8777 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386524.pdf [firstpage_image] =>[orig_patent_app_number] => 869668 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/869668
System for accessing information in a data processing system Apr 15, 1992 Issued
Array ( [id] => 3428037 [patent_doc_number] => 05394533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Cache system having only entries near block boundaries' [patent_app_type] => 1 [patent_app_number] => 7/869699 [patent_app_country] => US [patent_app_date] => 1992-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4919 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394533.pdf [firstpage_image] =>[orig_patent_app_number] => 869699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/869699
Cache system having only entries near block boundaries Apr 15, 1992 Issued
Array ( [id] => 3433279 [patent_doc_number] => 05390308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Method and apparatus for address mapping of dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 7/869529 [patent_app_country] => US [patent_app_date] => 1992-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5485 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390308.pdf [firstpage_image] =>[orig_patent_app_number] => 869529 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/869529
Method and apparatus for address mapping of dynamic random access memory Apr 14, 1992 Issued
07/860527 DATA REFERENCING SYSTEM Mar 29, 1992 Abandoned
Array ( [id] => 2977149 [patent_doc_number] => 05265227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Parallel protection checking in an address translation look-aside buffer' [patent_app_type] => 1 [patent_app_number] => 7/853008 [patent_app_country] => US [patent_app_date] => 1992-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265227.pdf [firstpage_image] =>[orig_patent_app_number] => 853008 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/853008
Parallel protection checking in an address translation look-aside buffer Mar 16, 1992 Issued
Array ( [id] => 3044440 [patent_doc_number] => 05329489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'DRAM having exclusively enabled column buffer blocks' [patent_app_type] => 1 [patent_app_number] => 7/852939 [patent_app_country] => US [patent_app_date] => 1992-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3097 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329489.pdf [firstpage_image] =>[orig_patent_app_number] => 852939 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/852939
DRAM having exclusively enabled column buffer blocks Mar 12, 1992 Issued
Array ( [id] => 3127686 [patent_doc_number] => 05396607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Matrix address generator and multivalue gradation processor having the same' [patent_app_type] => 1 [patent_app_number] => 7/848207 [patent_app_country] => US [patent_app_date] => 1992-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 9767 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396607.pdf [firstpage_image] =>[orig_patent_app_number] => 848207 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/848207
Matrix address generator and multivalue gradation processor having the same Mar 9, 1992 Issued
07/841896 HIGH PERFORMANCE COMPUTER PIPELINE Feb 24, 1992 Abandoned
Array ( [id] => 3532705 [patent_doc_number] => 05490257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'RAM based FIFO memory half-full detection apparatus and method' [patent_app_type] => 1 [patent_app_number] => 7/840024 [patent_app_country] => US [patent_app_date] => 1992-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2985 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490257.pdf [firstpage_image] =>[orig_patent_app_number] => 840024 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/840024
RAM based FIFO memory half-full detection apparatus and method Feb 23, 1992 Issued
07/837388 CACHE MEMORY FOR EFFICIENT ACCESS WITH ADDRESS SELECTORS Feb 18, 1992 Abandoned
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