Search

Bhisma Mehta

Supervisory Patent Examiner (ID: 1145, Phone: (571)272-3383 , Office: P/3763 )

Most Active Art Unit
3767
Art Unit(s)
3306, 3767, 3734, 3783, 3763
Total Applications
544
Issued Applications
260
Pending Applications
69
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3028423 [patent_doc_number] => 05341488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus' [patent_app_type] => 1 [patent_app_number] => 7/837555 [patent_app_country] => US [patent_app_date] => 1992-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341488.pdf [firstpage_image] =>[orig_patent_app_number] => 837555 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/837555
N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus Feb 13, 1992 Issued
Array ( [id] => 3422149 [patent_doc_number] => 05444660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Sequential access memory and its operation method' [patent_app_type] => 1 [patent_app_number] => 7/834049 [patent_app_country] => US [patent_app_date] => 1992-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444660.pdf [firstpage_image] =>[orig_patent_app_number] => 834049 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/834049
Sequential access memory and its operation method Feb 10, 1992 Issued
Array ( [id] => 3486698 [patent_doc_number] => 05428760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Circuitry and method for sharing internal microcontroller memory with an external processor' [patent_app_type] => 1 [patent_app_number] => 7/831896 [patent_app_country] => US [patent_app_date] => 1992-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4821 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428760.pdf [firstpage_image] =>[orig_patent_app_number] => 831896 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/831896
Circuitry and method for sharing internal microcontroller memory with an external processor Feb 5, 1992 Issued
Array ( [id] => 3111433 [patent_doc_number] => 05315550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Dynamic random access memory having sense amplifier activation delayed based on operation supply voltage and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 7/829144 [patent_app_country] => US [patent_app_date] => 1992-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11582 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315550.pdf [firstpage_image] =>[orig_patent_app_number] => 829144 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/829144
Dynamic random access memory having sense amplifier activation delayed based on operation supply voltage and operating method thereof Jan 30, 1992 Issued
Array ( [id] => 3463092 [patent_doc_number] => 05379258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Circuit for repairing defective bit in semiconductor memory device and repairing method' [patent_app_type] => 1 [patent_app_number] => 7/828254 [patent_app_country] => US [patent_app_date] => 1992-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13783 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379258.pdf [firstpage_image] =>[orig_patent_app_number] => 828254 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/828254
Circuit for repairing defective bit in semiconductor memory device and repairing method Jan 29, 1992 Issued
Array ( [id] => 3069230 [patent_doc_number] => 05357619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Paged memory scheme' [patent_app_type] => 1 [patent_app_number] => 7/819267 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2142 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357619.pdf [firstpage_image] =>[orig_patent_app_number] => 819267 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819267
Paged memory scheme Jan 9, 1992 Issued
Array ( [id] => 3460104 [patent_doc_number] => 05386523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Addressing scheme for accessing a portion of a large memory space' [patent_app_type] => 1 [patent_app_number] => 7/818607 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3763 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386523.pdf [firstpage_image] =>[orig_patent_app_number] => 818607 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/818607
Addressing scheme for accessing a portion of a large memory space Jan 9, 1992 Issued
Array ( [id] => 3437763 [patent_doc_number] => 05404474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Apparatus and method for addressing a variable sized block of memory' [patent_app_type] => 1 [patent_app_number] => 7/819393 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404474.pdf [firstpage_image] =>[orig_patent_app_number] => 819393 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819393
Apparatus and method for addressing a variable sized block of memory Jan 9, 1992 Issued
Array ( [id] => 3021153 [patent_doc_number] => 05355463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Circuit configuration for transforming the logical address space of a processor unit to the physical address space of a memory' [patent_app_type] => 1 [patent_app_number] => 7/818539 [patent_app_country] => US [patent_app_date] => 1992-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2317 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355463.pdf [firstpage_image] =>[orig_patent_app_number] => 818539 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/818539
Circuit configuration for transforming the logical address space of a processor unit to the physical address space of a memory Jan 8, 1992 Issued
Array ( [id] => 3497396 [patent_doc_number] => 05426748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Guest/host extended addressing method and means with contiguous access list entries' [patent_app_type] => 1 [patent_app_number] => 7/816911 [patent_app_country] => US [patent_app_date] => 1992-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13365 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426748.pdf [firstpage_image] =>[orig_patent_app_number] => 816911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/816911
Guest/host extended addressing method and means with contiguous access list entries Jan 2, 1992 Issued
07/815459 PREDICTIVE ADDRESSING ARCHITECTURE Dec 30, 1991 Abandoned
Array ( [id] => 3460091 [patent_doc_number] => 05386522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Dynamic physical address aliasing during program debugging' [patent_app_type] => 1 [patent_app_number] => 7/815734 [patent_app_country] => US [patent_app_date] => 1991-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2691 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386522.pdf [firstpage_image] =>[orig_patent_app_number] => 815734 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815734
Dynamic physical address aliasing during program debugging Dec 29, 1991 Issued
Array ( [id] => 2989488 [patent_doc_number] => 05253200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Electrically erasable and programmable read only memory using stacked-gate cell' [patent_app_type] => 1 [patent_app_number] => 7/814582 [patent_app_country] => US [patent_app_date] => 1991-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5652 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/253/05253200.pdf [firstpage_image] =>[orig_patent_app_number] => 814582 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/814582
Electrically erasable and programmable read only memory using stacked-gate cell Dec 29, 1991 Issued
Array ( [id] => 3064518 [patent_doc_number] => 05325496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Selectable pointer validation in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/813947 [patent_app_country] => US [patent_app_date] => 1991-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4389 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325496.pdf [firstpage_image] =>[orig_patent_app_number] => 813947 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/813947
Selectable pointer validation in a computer system Dec 23, 1991 Issued
Array ( [id] => 3465177 [patent_doc_number] => 05379392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Method of and apparatus for rapidly loading addressing registers' [patent_app_type] => 1 [patent_app_number] => 7/809386 [patent_app_country] => US [patent_app_date] => 1991-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5666 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379392.pdf [firstpage_image] =>[orig_patent_app_number] => 809386 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/809386
Method of and apparatus for rapidly loading addressing registers Dec 16, 1991 Issued
Array ( [id] => 3130515 [patent_doc_number] => 05381363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method and circuitry for performing a hidden read-modify-write' [patent_app_type] => 1 [patent_app_number] => 7/807134 [patent_app_country] => US [patent_app_date] => 1991-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3105 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381363.pdf [firstpage_image] =>[orig_patent_app_number] => 807134 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807134
Method and circuitry for performing a hidden read-modify-write Dec 11, 1991 Issued
07/800716 INFORMATION RECORDING DEVICE AND INFORMATION RECORDING AND REPRODUCING PROCESS Dec 2, 1991 Abandoned
Array ( [id] => 3086478 [patent_doc_number] => 05297085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Semiconductor memory device with redundant block and cell array' [patent_app_type] => 1 [patent_app_number] => 7/800701 [patent_app_country] => US [patent_app_date] => 1991-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6450 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297085.pdf [firstpage_image] =>[orig_patent_app_number] => 800701 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/800701
Semiconductor memory device with redundant block and cell array Dec 1, 1991 Issued
07/799728 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA TRANSFER THEREFOR Nov 21, 1991 Abandoned
Array ( [id] => 3107483 [patent_doc_number] => 05299161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method and device for improving performance of a parallel write test of a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/794631 [patent_app_country] => US [patent_app_date] => 1991-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/299/05299161.pdf [firstpage_image] =>[orig_patent_app_number] => 794631 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/794631
Method and device for improving performance of a parallel write test of a semiconductor memory device Nov 17, 1991 Issued
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