Search

Bijan Ahvazi

Examiner (ID: 5391, Phone: (571)270-3449 , Office: P/1763 )

Most Active Art Unit
1763
Art Unit(s)
1763, 4171, 1796, 1761
Total Applications
1564
Issued Applications
984
Pending Applications
107
Abandoned Applications
491

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 442891 [patent_doc_number] => 07256137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method of forming contact plug on silicide structure' [patent_app_type] => utility [patent_app_number] => 11/052938 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3664 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256137.pdf [firstpage_image] =>[orig_patent_app_number] => 11052938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052938
Method of forming contact plug on silicide structure Feb 6, 2005 Issued
Array ( [id] => 5869094 [patent_doc_number] => 20060163711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method to form an electronic device' [patent_app_type] => utility [patent_app_number] => 11/042227 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4407 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163711.pdf [firstpage_image] =>[orig_patent_app_number] => 11042227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042227
Method to form an electronic device Jan 23, 2005 Abandoned
Array ( [id] => 5596447 [patent_doc_number] => 20060160364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Refreshing wafers having low-k dielectric materials' [patent_app_type] => utility [patent_app_number] => 11/037647 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6638 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160364.pdf [firstpage_image] =>[orig_patent_app_number] => 11037647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037647
Refreshing wafers having low-k dielectric materials Jan 17, 2005 Issued
Array ( [id] => 263650 [patent_doc_number] => 07569414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'CMOS imager with integrated non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/034165 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3775 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569414.pdf [firstpage_image] =>[orig_patent_app_number] => 11034165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034165
CMOS imager with integrated non-volatile memory Jan 11, 2005 Issued
Array ( [id] => 6939243 [patent_doc_number] => 20050112806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby' [patent_app_type] => utility [patent_app_number] => 11/024777 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7677 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112806.pdf [firstpage_image] =>[orig_patent_app_number] => 11024777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024777
Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby Dec 29, 2004 Issued
Array ( [id] => 907147 [patent_doc_number] => 07332421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Method of fabricating gate electrode of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/024437 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332421.pdf [firstpage_image] =>[orig_patent_app_number] => 11024437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024437
Method of fabricating gate electrode of semiconductor device Dec 29, 2004 Issued
Array ( [id] => 7253683 [patent_doc_number] => 20050142823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of fabricating gate electrode of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/026287 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1974 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142823.pdf [firstpage_image] =>[orig_patent_app_number] => 11026287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026287
Method of fabricating gate electrode of semiconductor device Dec 29, 2004 Issued
Array ( [id] => 432228 [patent_doc_number] => 07265001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Methods of fabricating semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/025377 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265001.pdf [firstpage_image] =>[orig_patent_app_number] => 11025377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025377
Methods of fabricating semiconductor devices Dec 27, 2004 Issued
Array ( [id] => 6944876 [patent_doc_number] => 20050196925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method of forming stress-relaxed SiGe buffer layer' [patent_app_type] => utility [patent_app_number] => 11/018647 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196925.pdf [firstpage_image] =>[orig_patent_app_number] => 11018647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018647
Method of forming stress-relaxed SiGe buffer layer Dec 21, 2004 Abandoned
Array ( [id] => 6905717 [patent_doc_number] => 20050101112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Methods of nanotubes films and articles' [patent_app_type] => utility [patent_app_number] => 11/010491 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9272 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101112.pdf [firstpage_image] =>[orig_patent_app_number] => 11010491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010491
Methods of nanotubes films and articles Dec 12, 2004 Issued
Array ( [id] => 902861 [patent_doc_number] => 07335528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Methods of nanotube films and articles' [patent_app_type] => utility [patent_app_number] => 11/007752 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9290 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335528.pdf [firstpage_image] =>[orig_patent_app_number] => 11007752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/007752
Methods of nanotube films and articles Dec 7, 2004 Issued
Array ( [id] => 548538 [patent_doc_number] => 07164209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Methods of positioning and/or orienting nanostructures' [patent_app_type] => utility [patent_app_number] => 11/000557 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9514 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164209.pdf [firstpage_image] =>[orig_patent_app_number] => 11000557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000557
Methods of positioning and/or orienting nanostructures Nov 30, 2004 Issued
Array ( [id] => 475242 [patent_doc_number] => 07226875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method for enhancing FSG film stability' [patent_app_type] => utility [patent_app_number] => 10/999547 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4495 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/226/07226875.pdf [firstpage_image] =>[orig_patent_app_number] => 10999547 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999547
Method for enhancing FSG film stability Nov 29, 2004 Issued
Array ( [id] => 23707 [patent_doc_number] => 07795150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition' [patent_app_type] => utility [patent_app_number] => 10/998467 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3344 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795150.pdf [firstpage_image] =>[orig_patent_app_number] => 10998467 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998467
Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition Nov 28, 2004 Issued
Array ( [id] => 380067 [patent_doc_number] => 07309641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method for rounding bottom corners of trench and shallow trench isolation process' [patent_app_type] => utility [patent_app_number] => 10/997507 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1615 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309641.pdf [firstpage_image] =>[orig_patent_app_number] => 10997507 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997507
Method for rounding bottom corners of trench and shallow trench isolation process Nov 23, 2004 Issued
Array ( [id] => 5862393 [patent_doc_number] => 20060096523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method for producing crystals and screening crystallization conditions' [patent_app_type] => utility [patent_app_number] => 10/985307 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7861 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20060096523.pdf [firstpage_image] =>[orig_patent_app_number] => 10985307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985307
Method for producing crystals and screening crystallization conditions Nov 9, 2004 Issued
Array ( [id] => 531034 [patent_doc_number] => 07179738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Semiconductor assembly having substrate with electroplated contact pads' [patent_app_type] => utility [patent_app_number] => 10/985757 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3547 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/179/07179738.pdf [firstpage_image] =>[orig_patent_app_number] => 10985757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985757
Semiconductor assembly having substrate with electroplated contact pads Nov 8, 2004 Issued
Array ( [id] => 6915461 [patent_doc_number] => 20050093022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Spacer chalcogenide memory device' [patent_app_type] => utility [patent_app_number] => 10/983437 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1994 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093022.pdf [firstpage_image] =>[orig_patent_app_number] => 10983437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/983437
Spacer chalcogenide memory device Nov 7, 2004 Issued
Array ( [id] => 7097982 [patent_doc_number] => 20050130441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Semiconductor devices and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/981987 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1519 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130441.pdf [firstpage_image] =>[orig_patent_app_number] => 10981987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981987
Semiconductor devices and methods of manufacturing the same Nov 4, 2004 Issued
Array ( [id] => 428587 [patent_doc_number] => 07268021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Lead frame and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/981417 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268021.pdf [firstpage_image] =>[orig_patent_app_number] => 10981417 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981417
Lead frame and method of manufacturing the same Nov 3, 2004 Issued
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