
Bilkis Jahan
Examiner (ID: 17029, Phone: (571)270-5022 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 4122, 2817, 2814, 2896, 2816, 2809 |
| Total Applications | 1252 |
| Issued Applications | 1052 |
| Pending Applications | 108 |
| Abandoned Applications | 119 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19470536
[patent_doc_number] => 20240324206
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => NONVOLATILE MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/581174
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13571
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581174
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/581174 | NONVOLATILE MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME | Feb 18, 2024 | Pending |
Array
(
[id] => 19221569
[patent_doc_number] => 20240186273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/444066
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5652
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444066
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444066 | SEMICONDUCTOR DEVICE | Feb 15, 2024 | Pending |
Array
(
[id] => 19237470
[patent_doc_number] => 20240194665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/443779
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443779
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443779 | Semiconductor chip, semiconductor device and manufacturing method of semiconductor device | Feb 15, 2024 | Issued |
Array
(
[id] => 20103131
[patent_doc_number] => 20250233067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/442962
[patent_app_country] => US
[patent_app_date] => 2024-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442962
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/442962 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF | Feb 14, 2024 | Pending |
Array
(
[id] => 20332830
[patent_doc_number] => 12463115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-04
[patent_title] => Electrostatic discharge protection circuit
[patent_app_type] => utility
[patent_app_number] => 18/442671
[patent_app_country] => US
[patent_app_date] => 2024-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 21
[patent_no_of_words] => 1095
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442671
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/442671 | Electrostatic discharge protection circuit | Feb 14, 2024 | Issued |
Array
(
[id] => 20047107
[patent_doc_number] => 20250185329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => SELECTIVE FORMATION OF ETCH STOP LAYERS AND THE STRUCTURES THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/442747
[patent_app_country] => US
[patent_app_date] => 2024-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442747
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/442747 | SELECTIVE FORMATION OF ETCH STOP LAYERS AND THE STRUCTURES THEREOF | Feb 14, 2024 | Pending |
Array
(
[id] => 20167880
[patent_doc_number] => 20250259927
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-14
[patent_title] => FUSIBLE D-FUSE HYBRID BOND STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/440929
[patent_app_country] => US
[patent_app_date] => 2024-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6799
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440929
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/440929 | FUSIBLE D-FUSE HYBRID BOND STRUCTURE | Feb 12, 2024 | Pending |
Array
(
[id] => 20141057
[patent_doc_number] => 20250248101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => TOP SACRIFICIAL RIBBON STRUCTURE FOR GATE ALL AROUND DEVICE ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 18/429045
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2151
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429045
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/429045 | TOP SACRIFICIAL RIBBON STRUCTURE FOR GATE ALL AROUND DEVICE ARCHITECTURE | Jan 30, 2024 | Pending |
Array
(
[id] => 20013149
[patent_doc_number] => 20250151371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
[patent_app_type] => utility
[patent_app_number] => 18/428603
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428603
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428603 | SEMICONDUCTOR DEVICE AND METHODS OF FORMATION | Jan 30, 2024 | Pending |
Array
(
[id] => 20831511
[patent_doc_number] => 12685115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-14
[patent_title] => Growth suppression deposition for CVD tungsten gap fill with thermal treatment
[patent_app_type] => utility
[patent_app_number] => 18/425408
[patent_app_country] => US
[patent_app_date] => 2024-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 2443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425408
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/425408 | Growth suppression deposition for CVD tungsten gap fill with thermal treatment | Jan 28, 2024 | Issued |
Array
(
[id] => 19546560
[patent_doc_number] => 20240363596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/415183
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12360
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415183
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415183 | DISPLAY DEVICE | Jan 16, 2024 | Pending |
Array
(
[id] => 19407296
[patent_doc_number] => 20240290807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => SUBSTRATELESS CHIP SCALE OPTICAL SENSOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/415231
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3363
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415231
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415231 | SUBSTRATELESS CHIP SCALE OPTICAL SENSOR PACKAGE | Jan 16, 2024 | Pending |
Array
(
[id] => 19161243
[patent_doc_number] => 20240153950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/413869
[patent_app_country] => US
[patent_app_date] => 2024-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413869
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/413869 | Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit | Jan 15, 2024 | Issued |
Array
(
[id] => 20375328
[patent_doc_number] => 12482772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Bonding structure of dies with dangling bonds
[patent_app_type] => utility
[patent_app_number] => 18/411674
[patent_app_country] => US
[patent_app_date] => 2024-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 33
[patent_no_of_words] => 2080
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411674
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/411674 | Bonding structure of dies with dangling bonds | Jan 11, 2024 | Issued |
Array
(
[id] => 20096415
[patent_doc_number] => 20250226351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => SEMICONDUCTOR PACKAGE WITH HEAT FLOW RESTRICTING CONNECTOR
[patent_app_type] => utility
[patent_app_number] => 18/407918
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5652
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407918
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407918 | SEMICONDUCTOR PACKAGE WITH HEAT FLOW RESTRICTING CONNECTOR | Jan 8, 2024 | Pending |
Array
(
[id] => 19161174
[patent_doc_number] => 20240153881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => System on Integrated Chips (SoIC) and Semiconductor Structures with Integrated SoIC
[patent_app_type] => utility
[patent_app_number] => 18/402061
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13023
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402061
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402061 | System on Integrated Chips (SoIC) and Semiconductor Structures with Integrated SoIC | Jan 1, 2024 | Pending |
Array
(
[id] => 19539522
[patent_doc_number] => 12132079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Bonding and isolation techniques for stacked transistor structures
[patent_app_type] => utility
[patent_app_number] => 18/392379
[patent_app_country] => US
[patent_app_date] => 2023-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 21266
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392379
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/392379 | Bonding and isolation techniques for stacked transistor structures | Dec 20, 2023 | Issued |
Array
(
[id] => 20074237
[patent_doc_number] => 20250212459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 18/391056
[patent_app_country] => US
[patent_app_date] => 2023-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391056
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/391056 | METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS | Dec 19, 2023 | Pending |
Array
(
[id] => 19071294
[patent_doc_number] => 20240105720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/525909
[patent_app_country] => US
[patent_app_date] => 2023-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525909
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/525909 | Semiconductor device and method for fabricating the same | Nov 30, 2023 | Issued |
Array
(
[id] => 20036270
[patent_doc_number] => 20250174492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => INTERCONNECTION STRUCTURE HAVING AIR GAP
[patent_app_type] => utility
[patent_app_number] => 18/523286
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523286
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/523286 | INTERCONNECTION STRUCTURE HAVING AIR GAP | Nov 28, 2023 | Pending |