Search

Bilkis Jahan

Examiner (ID: 16855, Phone: (571)270-5022 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2809, 2896, 2814, 2816, 4122
Total Applications
1200
Issued Applications
1021
Pending Applications
107
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9796597 [patent_doc_number] => 20150008541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'MEMS PRESSURE SENSORS AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/095155 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/095155
MEMS pressure sensors and fabrication method thereof Dec 2, 2013 Issued
Array ( [id] => 9542505 [patent_doc_number] => 20140167152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Reduced Gate Charge Trench Field-Effect Transistor' [patent_app_type] => utility [patent_app_number] => 14/095063 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/095063
Reduced Gate Charge Trench Field-Effect Transistor Dec 2, 2013 Abandoned
Array ( [id] => 9754064 [patent_doc_number] => 20140284764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING HEAT SLUG AND PASSIVE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/095998 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095998 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/095998
Semiconductor package having heat slug and passive device Dec 2, 2013 Issued
Array ( [id] => 9515349 [patent_doc_number] => 20140151841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING A POSITIVE-BEVEL TERMINATION OR A NEGATIVE-BEVEL TERMINATION AND THEIR MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/094189 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3989 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/094189
SEMICONDUCTOR DEVICES HAVING A POSITIVE-BEVEL TERMINATION OR A NEGATIVE-BEVEL TERMINATION AND THEIR MANUFACTURE Dec 1, 2013 Abandoned
Array ( [id] => 9923373 [patent_doc_number] => 08981342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Light emitting diode with three-dimensional nano-structures on a semiconductor layer and an active layer' [patent_app_type] => utility [patent_app_number] => 14/093692 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5667 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093692
Light emitting diode with three-dimensional nano-structures on a semiconductor layer and an active layer Dec 1, 2013 Issued
Array ( [id] => 10590651 [patent_doc_number] => 09312273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition' [patent_app_type] => utility [patent_app_number] => 14/093646 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4570 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093646
Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition Dec 1, 2013 Issued
Array ( [id] => 10971785 [patent_doc_number] => 20140374820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'DUAL TRENCH MOS TRANSISTOR AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/093596 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4958 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093596
Dual trench MOS transistor and method for forming the same Dec 1, 2013 Issued
Array ( [id] => 9790767 [patent_doc_number] => 20150002712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF FABRICATING THE SAME, AND CAMERA MODULE' [patent_app_type] => utility [patent_app_number] => 14/093632 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5430 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093632
Solid-state image pickup device, and camera module Dec 1, 2013 Issued
Array ( [id] => 10132121 [patent_doc_number] => 09165962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Solid state imaging device' [patent_app_type] => utility [patent_app_number] => 14/093642 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5855 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093642 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093642
Solid state imaging device Dec 1, 2013 Issued
Array ( [id] => 10525707 [patent_doc_number] => 09252228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator' [patent_app_type] => utility [patent_app_number] => 14/093105 [patent_app_country] => US [patent_app_date] => 2013-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2295 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093105
Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator Nov 28, 2013 Issued
Array ( [id] => 10035436 [patent_doc_number] => 09076762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Contact structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/093268 [patent_app_country] => US [patent_app_date] => 2013-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093268
Contact structure of semiconductor device Nov 28, 2013 Issued
Array ( [id] => 9875124 [patent_doc_number] => 08962391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Method of fabricating a wafer level chip scale package without an encapsulated via' [patent_app_type] => utility [patent_app_number] => 14/091040 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3660 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091040
Method of fabricating a wafer level chip scale package without an encapsulated via Nov 25, 2013 Issued
Array ( [id] => 9778639 [patent_doc_number] => 08853846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Semiconductor device and a manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 14/072047 [patent_app_country] => US [patent_app_date] => 2013-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 67 [patent_no_of_words] => 27120 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/072047
Semiconductor device and a manufacturing method of the same Nov 4, 2013 Issued
Array ( [id] => 9327861 [patent_doc_number] => 20140054643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/070433 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5256 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/070433
Electrostatic discharge protection device Oct 31, 2013 Issued
Array ( [id] => 9824001 [patent_doc_number] => 08933487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Controlling lateral two-dimensional electron hole gas HEMT in type III nitride devices using ion implantation through gray scale mask' [patent_app_type] => utility [patent_app_number] => 14/063207 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2706 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063207 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/063207
Controlling lateral two-dimensional electron hole gas HEMT in type III nitride devices using ion implantation through gray scale mask Oct 24, 2013 Issued
Array ( [id] => 9711409 [patent_doc_number] => 08835983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Nitride semiconductor device including a doped nitride semiconductor between upper and lower nitride semiconductor layers' [patent_app_type] => utility [patent_app_number] => 14/062699 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 11155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062699
Nitride semiconductor device including a doped nitride semiconductor between upper and lower nitride semiconductor layers Oct 23, 2013 Issued
Array ( [id] => 15286559 [patent_doc_number] => 10515949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Integrated circuit and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 14/056725 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056725 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056725
Integrated circuit and manufacturing method thereof Oct 16, 2013 Issued
Array ( [id] => 9360436 [patent_doc_number] => 20140070308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/028017 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 25870 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028017
Semiconductor device Sep 15, 2013 Issued
Array ( [id] => 12375798 [patent_doc_number] => 09960160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process [patent_app_type] => utility [patent_app_number] => 14/013960 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2904 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013960 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/013960
Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process Aug 28, 2013 Issued
Array ( [id] => 9728898 [patent_doc_number] => 20140264605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Hybrid ETSOI Structure to Minimize Noise Coupling from TSV' [patent_app_type] => utility [patent_app_number] => 13/961003 [patent_app_country] => US [patent_app_date] => 2013-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4149 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13961003 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/961003
Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV Aug 6, 2013 Issued
Menu