Search

Binh C. Tat

Examiner (ID: 10573, Phone: (571)272-1908 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1673
Issued Applications
1410
Pending Applications
98
Abandoned Applications
189

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17388134 [patent_doc_number] => 20220035986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SUPERSEDING DESIGN RULE CHECK (DRC) RULES IN A DRC-CORRECT INTERACTIVE ROUTER [patent_app_type] => utility [patent_app_number] => 17/393079 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393079
Superseding design rule check (DRC) rules in a DRC-correct interactive router Aug 2, 2021 Issued
Array ( [id] => 18873476 [patent_doc_number] => 11861287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Integrated circuit development using density-aware border fill [patent_app_type] => utility [patent_app_number] => 17/391117 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391117
Integrated circuit development using density-aware border fill Aug 1, 2021 Issued
Array ( [id] => 17492534 [patent_doc_number] => 11281839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Method, apparatus and electronic device for photolithographic mask optimization of joint optimization of pattern and image [patent_app_type] => utility [patent_app_number] => 17/389496 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389496
Method, apparatus and electronic device for photolithographic mask optimization of joint optimization of pattern and image Jul 29, 2021 Issued
Array ( [id] => 18181330 [patent_doc_number] => 20230042059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => FAST INDEPENDENT CHECKER FOR EXTREME ULTRAVIOLET (EUV) ROUTING [patent_app_type] => utility [patent_app_number] => 17/389860 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389860
Fast independent checker for extreme ultraviolet (EUV) routing Jul 29, 2021 Issued
Array ( [id] => 18720390 [patent_doc_number] => 11797736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => SARO: scalable attack-resistant obfuscation of logic circuits [patent_app_type] => utility [patent_app_number] => 17/443815 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5514 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443815
SARO: scalable attack-resistant obfuscation of logic circuits Jul 26, 2021 Issued
Array ( [id] => 18527956 [patent_doc_number] => 11714950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Automated timing closure on circuit designs [patent_app_type] => utility [patent_app_number] => 17/382621 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382621
Automated timing closure on circuit designs Jul 21, 2021 Issued
Array ( [id] => 18561159 [patent_doc_number] => 11726402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Method and system for layout enhancement based on inter-cell correlation [patent_app_type] => utility [patent_app_number] => 17/383287 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/383287
Method and system for layout enhancement based on inter-cell correlation Jul 21, 2021 Issued
Array ( [id] => 17984912 [patent_doc_number] => 20220350949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => TECHNOLOGY FILE PROCESS RULE VALIDATION [patent_app_type] => utility [patent_app_number] => 17/381499 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381499
Technology file process rule validation Jul 20, 2021 Issued
Array ( [id] => 18592387 [patent_doc_number] => 11741287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => Prioritized mask correction [patent_app_type] => utility [patent_app_number] => 17/370990 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 12928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370990
Prioritized mask correction Jul 7, 2021 Issued
Array ( [id] => 18934355 [patent_doc_number] => 11886789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-30 [patent_title] => Block design containers for circuit design [patent_app_type] => utility [patent_app_number] => 17/369192 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 16531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369192
Block design containers for circuit design Jul 6, 2021 Issued
Array ( [id] => 18122959 [patent_doc_number] => 20230008569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SYSTEM MEMORY-AWARE CIRCUIT REGION PARTITIONING [patent_app_type] => utility [patent_app_number] => 17/369329 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369329
System memory-aware circuit region partitioning Jul 6, 2021 Issued
Array ( [id] => 18644918 [patent_doc_number] => 11768990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-26 [patent_title] => Interconnect flow graph for integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/305043 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305043
Interconnect flow graph for integrated circuit design Jun 28, 2021 Issued
Array ( [id] => 19045652 [patent_doc_number] => 11934764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Routing and manufacturing with a minimum area metal structure [patent_app_type] => utility [patent_app_number] => 17/362662 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362662
Routing and manufacturing with a minimum area metal structure Jun 28, 2021 Issued
Array ( [id] => 18728244 [patent_doc_number] => 20230342537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => LAYOUT DESIGN METHOD, INTEGRATED CIRCUIT, OPERATION CHIP, AND COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/245466 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245466
LAYOUT DESIGN METHOD, INTEGRATED CIRCUIT, OPERATION CHIP, AND COMPUTING DEVICE Jun 23, 2021 Pending
Array ( [id] => 19427100 [patent_doc_number] => 12086522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method of generating netlist including proximity-effect-inducer (PEI) parameters [patent_app_type] => utility [patent_app_number] => 17/353991 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 15236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353991
Method of generating netlist including proximity-effect-inducer (PEI) parameters Jun 21, 2021 Issued
Array ( [id] => 19015340 [patent_doc_number] => 11922275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => System and method for determining a perturbation energy of a quantum state of a many-body system [patent_app_type] => utility [patent_app_number] => 17/351873 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351873
System and method for determining a perturbation energy of a quantum state of a many-body system Jun 17, 2021 Issued
Array ( [id] => 18890979 [patent_doc_number] => 11869756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Virtual metrology enhanced plasma process optimization method [patent_app_type] => utility [patent_app_number] => 17/350439 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350439
Virtual metrology enhanced plasma process optimization method Jun 16, 2021 Issued
Array ( [id] => 17114363 [patent_doc_number] => 20210294960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SYSTEMS AND METHODS FOR INTELLIGENTLY BUFFER TRACKING FOR OPTIMIZED DATAFLOW WITHIN AN INTEGRATED CIRCUIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/339291 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339291
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture Jun 3, 2021 Issued
Array ( [id] => 17261336 [patent_doc_number] => 20210374321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SYSTEM AND METHOD FOR PROVIDING ENHANCED NET PRUNING [patent_app_type] => utility [patent_app_number] => 17/334495 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334495
System and method for providing enhanced net pruning May 27, 2021 Issued
Array ( [id] => 18577955 [patent_doc_number] => 11734488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => System and method to process a virtual partition cell injected into a hierarchical integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/330018 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330018
System and method to process a virtual partition cell injected into a hierarchical integrated circuit design May 24, 2021 Issued
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