Search

Binh C. Tat

Examiner (ID: 10573, Phone: (571)272-1908 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1673
Issued Applications
1410
Pending Applications
98
Abandoned Applications
189

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20110472 [patent_doc_number] => 12361196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => DRC test pattern generation method and apparatus, electronic device, and storage medium [patent_app_type] => utility [patent_app_number] => 17/658516 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4107 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658516
DRC test pattern generation method and apparatus, electronic device, and storage medium Apr 7, 2022 Issued
Array ( [id] => 17932290 [patent_doc_number] => 20220327415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => Optimized quantum transduction [patent_app_type] => utility [patent_app_number] => 17/715748 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715748 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715748
Optimized quantum transduction Apr 6, 2022 Pending
Array ( [id] => 17916085 [patent_doc_number] => 20220318481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => RUNTIME AND MEMORY EFFICIENT ATTRIBUTE QUERY HANDLING FOR DISTRIBUTED ENGINE [patent_app_type] => utility [patent_app_number] => 17/711371 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711371
Runtime and memory efficient attribute query handling for distributed engine Mar 31, 2022 Issued
Array ( [id] => 17916082 [patent_doc_number] => 20220318478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => METHOD, SYSTEM, APPARATUS, MEDIUM, AND PROGRAM FOR PHYSICAL DESIGN WIRING AND OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 17/708483 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708483
Method, system, apparatus, medium, and program for physical design wiring and optimization Mar 29, 2022 Issued
Array ( [id] => 17962472 [patent_doc_number] => 20220343053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR STRUCTURE OF CELL ARRAY WITH ADAPTIVE THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/708438 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708438
Semiconductor structure of cell array with adaptive threshold voltage Mar 29, 2022 Issued
Array ( [id] => 17736954 [patent_doc_number] => 20220222413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Apparatus, Device, Method and Computer Program for Generating a Circuit Design of Polynomial Interpolation Hardware [patent_app_type] => utility [patent_app_number] => 17/656438 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656438
Apparatus, device, method and computer program for generating a circuit design of polynomial interpolation hardware Mar 24, 2022 Issued
Array ( [id] => 19198153 [patent_doc_number] => 11995391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/702879 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702879
Semiconductor device and method of fabricating the same Mar 23, 2022 Issued
Array ( [id] => 17901599 [patent_doc_number] => 20220311261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => BATTERY MANAGEMENT SYSTEM AND BATTERY MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/695897 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695897
Battery management system and battery management method Mar 15, 2022 Issued
Array ( [id] => 17866320 [patent_doc_number] => 20220289055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => POSITIONING DEVICE FOR LOCATION POSITIONING OF ENERGY STORAGE CELLS [patent_app_type] => utility [patent_app_number] => 17/693347 [patent_app_country] => US [patent_app_date] => 2022-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693347
POSITIONING DEVICE FOR LOCATION POSITIONING OF ENERGY STORAGE CELLS Mar 11, 2022 Pending
Array ( [id] => 18795911 [patent_doc_number] => 11829700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Method of analyzing and detecting critical cells [patent_app_type] => utility [patent_app_number] => 17/690990 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690990
Method of analyzing and detecting critical cells Mar 8, 2022 Issued
Array ( [id] => 19917887 [patent_doc_number] => 12293257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Device with two superposed electrostatic control gate levels [patent_app_type] => utility [patent_app_number] => 17/654181 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 3360 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654181
Device with two superposed electrostatic control gate levels Mar 8, 2022 Issued
Array ( [id] => 19827960 [patent_doc_number] => 12248743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Cell architecture with backside power rails [patent_app_type] => utility [patent_app_number] => 17/685166 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685166
Cell architecture with backside power rails Mar 1, 2022 Issued
Array ( [id] => 19219509 [patent_doc_number] => 20240184213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHOD OF PATTERN SELECTION FOR A SEMICONDUCTOR MANUFACTURING RELATED PROCESS [patent_app_type] => utility [patent_app_number] => 18/278881 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18278881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/278881
METHOD OF PATTERN SELECTION FOR A SEMICONDUCTOR MANUFACTURING RELATED PROCESS Feb 27, 2022 Pending
Array ( [id] => 17738704 [patent_doc_number] => 20220224166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POWER TRANSMITTING APPARATUS, CONTROL METHOD FOR POWER TRANSMITTING APPARATUS, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/678880 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678880
Power transmitting apparatus, control method for power transmitting apparatus, and storage medium Feb 22, 2022 Issued
Array ( [id] => 18365635 [patent_doc_number] => 20230147226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SIZE SETTING METHOD FOR POWER SWITCH TRANSISTOR AND SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/676882 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676882
Size setting method for power switch transistor and system thereof Feb 21, 2022 Issued
Array ( [id] => 19950313 [patent_doc_number] => 12321678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Integrated circuit with compact layout arrangement [patent_app_type] => utility [patent_app_number] => 17/673755 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1293 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673755
Integrated circuit with compact layout arrangement Feb 15, 2022 Issued
Array ( [id] => 18554204 [patent_doc_number] => 20230252217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => RULE CHECK HEATMAP PREDICTION [patent_app_type] => utility [patent_app_number] => 17/650656 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650656
Rule check heatmap prediction Feb 9, 2022 Issued
Array ( [id] => 17613412 [patent_doc_number] => 20220155692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Optical Proximity Correction and Photomasks [patent_app_type] => utility [patent_app_number] => 17/665757 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665757
Optical proximity correction and photomasks Feb 6, 2022 Issued
Array ( [id] => 17812090 [patent_doc_number] => 20220263925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SYSTEM AND METHOD FOR SYNTHESIS OF CONNECTIVITY TO AN INTERCONNECT IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SoC) [patent_app_type] => utility [patent_app_number] => 17/665578 [patent_app_country] => US [patent_app_date] => 2022-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665578
System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC) Feb 5, 2022 Issued
Array ( [id] => 18555790 [patent_doc_number] => 20230253807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => Battery and Charging Case [patent_app_type] => utility [patent_app_number] => 17/665344 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665344
Battery and Charging Case Feb 3, 2022 Pending
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