Search

Binh X. Tran

Examiner (ID: 14481, Phone: (571)272-1469 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1713, 1792, 1765
Total Applications
1675
Issued Applications
1301
Pending Applications
123
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5790198 [patent_doc_number] => 20060011588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Silicon wafer etching process and composition' [patent_app_type] => utility [patent_app_number] => 11/152362 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20060011588.pdf [firstpage_image] =>[orig_patent_app_number] => 11152362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152362
Silicon wafer etching process and composition Jun 13, 2005 Issued
Array ( [id] => 923102 [patent_doc_number] => 07319074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Method of defining polysilicon patterns' [patent_app_type] => utility [patent_app_number] => 11/160178 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1815 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319074.pdf [firstpage_image] =>[orig_patent_app_number] => 11160178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160178
Method of defining polysilicon patterns Jun 12, 2005 Issued
Array ( [id] => 380081 [patent_doc_number] => 07309656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method for forming step channel of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/148558 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1634 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309656.pdf [firstpage_image] =>[orig_patent_app_number] => 11148558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148558
Method for forming step channel of semiconductor device Jun 8, 2005 Issued
Array ( [id] => 6966687 [patent_doc_number] => 20050233584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor device having a contact window including a lower with a wider to provide a lower contact resistance' [patent_app_type] => utility [patent_app_number] => 11/149571 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7491 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233584.pdf [firstpage_image] =>[orig_patent_app_number] => 11149571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149571
Semiconductor device having a contact window including a lower with a wider to provide a lower contact resistance Jun 8, 2005 Issued
Array ( [id] => 577021 [patent_doc_number] => 07456113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Cleaning method and solution for cleaning a wafer in a single wafer process' [patent_app_type] => utility [patent_app_number] => 11/146574 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 11136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456113.pdf [firstpage_image] =>[orig_patent_app_number] => 11146574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/146574
Cleaning method and solution for cleaning a wafer in a single wafer process Jun 5, 2005 Issued
Array ( [id] => 5767381 [patent_doc_number] => 20060019201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Post-dry etching cleaning liquid composition and process for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/145731 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10717 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019201.pdf [firstpage_image] =>[orig_patent_app_number] => 11145731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145731
Post-dry etching cleaning liquid composition and process for fabricating semiconductor device Jun 5, 2005 Abandoned
Array ( [id] => 578572 [patent_doc_number] => 07449127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Cleaning method and solution for cleaning a wafer in a single wafer process' [patent_app_type] => utility [patent_app_number] => 11/145304 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 8773 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449127.pdf [firstpage_image] =>[orig_patent_app_number] => 11145304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145304
Cleaning method and solution for cleaning a wafer in a single wafer process Jun 2, 2005 Issued
Array ( [id] => 63808 [patent_doc_number] => 07759251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Dual damascene integration structure and method for forming improved dual damascene integration structure' [patent_app_type] => utility [patent_app_number] => 11/143421 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 6876 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759251.pdf [firstpage_image] =>[orig_patent_app_number] => 11143421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/143421
Dual damascene integration structure and method for forming improved dual damascene integration structure Jun 1, 2005 Issued
Array ( [id] => 4927507 [patent_doc_number] => 20080166870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Fabrication of Interconnect Structures' [patent_app_type] => utility [patent_app_number] => 11/570014 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4240 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166870.pdf [firstpage_image] =>[orig_patent_app_number] => 11570014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/570014
Fabrication of Interconnect Structures May 22, 2005 Abandoned
Array ( [id] => 7702543 [patent_doc_number] => 08088296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Plasma processing device and plasma processing method' [patent_app_type] => utility [patent_app_number] => 11/574570 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3909 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/088/08088296.pdf [firstpage_image] =>[orig_patent_app_number] => 11574570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/574570
Plasma processing device and plasma processing method May 18, 2005 Issued
Array ( [id] => 7019580 [patent_doc_number] => 20050221599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Etching method, semiconductor and fabricating method for the same' [patent_app_type] => utility [patent_app_number] => 11/131180 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22502 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221599.pdf [firstpage_image] =>[orig_patent_app_number] => 11131180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131180
Etching method, semiconductor and fabricating method for the same May 17, 2005 Issued
Array ( [id] => 558073 [patent_doc_number] => 07470628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Etching methods' [patent_app_type] => utility [patent_app_number] => 11/130760 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4427 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470628.pdf [firstpage_image] =>[orig_patent_app_number] => 11130760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/130760
Etching methods May 16, 2005 Issued
Array ( [id] => 7108069 [patent_doc_number] => 20050205522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Chemical agent additives in copper CMP slurry' [patent_app_type] => utility [patent_app_number] => 11/130377 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3413 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205522.pdf [firstpage_image] =>[orig_patent_app_number] => 11130377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/130377
Chemical agent additives in copper CMP slurry May 15, 2005 Abandoned
Array ( [id] => 5823031 [patent_doc_number] => 20060060213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Manufacture of ultra-clean surfaces by selective' [patent_app_type] => utility [patent_app_number] => 11/128215 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060213.pdf [firstpage_image] =>[orig_patent_app_number] => 11128215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128215
Manufacture of ultra-clean surfaces by selective May 12, 2005 Abandoned
Array ( [id] => 5895006 [patent_doc_number] => 20060003545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method of making scratch resistant coated glass article including layer(s) resistant to fluoride-based etchant(s)' [patent_app_type] => utility [patent_app_number] => 11/120180 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5148 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003545.pdf [firstpage_image] =>[orig_patent_app_number] => 11120180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/120180
Method of making scratch resistant coated glass article including layer(s) resistant to fluoride-based etchant(s) May 2, 2005 Issued
Array ( [id] => 899970 [patent_doc_number] => 07338906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/114083 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1910 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/338/07338906.pdf [firstpage_image] =>[orig_patent_app_number] => 11114083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114083
Method for fabricating semiconductor device Apr 25, 2005 Issued
Array ( [id] => 849129 [patent_doc_number] => 07381647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Methods and systems for planarizing microelectronic devices with Ge-Se-Ag layers' [patent_app_type] => utility [patent_app_number] => 11/112787 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4605 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/381/07381647.pdf [firstpage_image] =>[orig_patent_app_number] => 11112787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/112787
Methods and systems for planarizing microelectronic devices with Ge-Se-Ag layers Apr 20, 2005 Issued
Array ( [id] => 383073 [patent_doc_number] => 07307025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-11 [patent_title] => 'Lag control' [patent_app_type] => utility [patent_app_number] => 11/104733 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5291 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307025.pdf [firstpage_image] =>[orig_patent_app_number] => 11104733 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/104733
Lag control Apr 11, 2005 Issued
Array ( [id] => 917095 [patent_doc_number] => 07323418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'Etch-back process for capping a polymer memory device' [patent_app_type] => utility [patent_app_number] => 11/102004 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323418.pdf [firstpage_image] =>[orig_patent_app_number] => 11102004 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/102004
Etch-back process for capping a polymer memory device Apr 7, 2005 Issued
Array ( [id] => 5874626 [patent_doc_number] => 20060166505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Integrated process for thin film resistors with silicides' [patent_app_type] => utility [patent_app_number] => 11/101891 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4058 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166505.pdf [firstpage_image] =>[orig_patent_app_number] => 11101891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101891
Integrated process for thin film resistors with silicides Apr 7, 2005 Issued
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