Search

Bitew A. Dinke

Examiner (ID: 17355, Phone: (571)272-0534 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2812, 2896, 2823, 2826
Total Applications
880
Issued Applications
575
Pending Applications
103
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15428009 [patent_doc_number] => 10546944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/823007 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5347 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823007 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823007
Semiconductor device and method of fabricating the same Nov 26, 2017 Issued
Array ( [id] => 15488665 [patent_doc_number] => 10559696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Hybrid CMOS device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/744811 [patent_app_country] => US [patent_app_date] => 2017-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6469 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 579 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15744811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/744811
Hybrid CMOS device and manufacturing method thereof Nov 24, 2017 Issued
Array ( [id] => 12263937 [patent_doc_number] => 20180083134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'BULK TO SILICON ON INSULATOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/819306 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 8175 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819306
Bulk to silicon on insulator device Nov 20, 2017 Issued
Array ( [id] => 15234559 [patent_doc_number] => 10505010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Semiconductor device blocking leakage current and method of forming the same [patent_app_type] => utility [patent_app_number] => 15/820171 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 90 [patent_no_of_words] => 12019 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820171
Semiconductor device blocking leakage current and method of forming the same Nov 20, 2017 Issued
Array ( [id] => 12918685 [patent_doc_number] => 20180198071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => INTERMETALLIC CONTACT FOR CARBON NANOTUBE FETS [patent_app_type] => utility [patent_app_number] => 15/803074 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803074
Intermetallic contact for carbon nanotube FETs Nov 2, 2017 Issued
Array ( [id] => 13543391 [patent_doc_number] => 20180323242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => Display With Nanostructure Angle-of-View Adjustment Structures [patent_app_type] => utility [patent_app_number] => 15/802256 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802256
Display with nanostructure angle-of-view adjustment structures Nov 1, 2017 Issued
Array ( [id] => 15062145 [patent_doc_number] => 10461387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Systems and methods for improved chip device performance [patent_app_type] => utility [patent_app_number] => 15/802270 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8463 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802270
Systems and methods for improved chip device performance Nov 1, 2017 Issued
Array ( [id] => 12692842 [patent_doc_number] => 20180122780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => CHIP PACKAGE STRUCTURE WITH MOLDING LAYER [patent_app_type] => utility [patent_app_number] => 15/801846 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801846
Chip package structure with molding layer Nov 1, 2017 Issued
Array ( [id] => 12188912 [patent_doc_number] => 20180047848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/796874 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4683 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796874
Method of fabricating semiconductor device Oct 29, 2017 Issued
Array ( [id] => 12849442 [patent_doc_number] => 20180174987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/794000 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794000
SEMICONDUCTOR DEVICE Oct 25, 2017 Abandoned
Array ( [id] => 14707425 [patent_doc_number] => 10381475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit [patent_app_type] => utility [patent_app_number] => 15/785677 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 11468 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785677 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785677
Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit Oct 16, 2017 Issued
Array ( [id] => 14191373 [patent_doc_number] => 20190115392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL) [patent_app_type] => utility [patent_app_number] => 15/784343 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784343
ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL) Oct 15, 2017 Abandoned
Array ( [id] => 12650202 [patent_doc_number] => 20180108565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => METHOD OF LASER-PROCESSING DEVICE WAFER [patent_app_type] => utility [patent_app_number] => 15/730940 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730940
Method of laser-processing device wafer Oct 11, 2017 Issued
Array ( [id] => 12631374 [patent_doc_number] => 20180102288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 15/725842 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725842
WAFER PROCESSING METHOD Oct 4, 2017 Abandoned
Array ( [id] => 14252585 [patent_doc_number] => 10276499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Dual power structure with connection pins [patent_app_type] => utility [patent_app_number] => 15/714172 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 8270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714172
Dual power structure with connection pins Sep 24, 2017 Issued
Array ( [id] => 17682151 [patent_doc_number] => 11366401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Photoconductive charge trapping apparatus [patent_app_type] => utility [patent_app_number] => 16/630273 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6814 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630273
Photoconductive charge trapping apparatus Sep 21, 2017 Issued
Array ( [id] => 13452233 [patent_doc_number] => 20180277659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => VERTICAL QUANTUM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/707258 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707258
Vertical quantum transistor Sep 17, 2017 Issued
Array ( [id] => 12122465 [patent_doc_number] => 20180006050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/704758 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 10757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704758 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704758
Semiconductor memory device and method for manufacturing same Sep 13, 2017 Issued
Array ( [id] => 15873565 [patent_doc_number] => 20200144186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => ACTIVE SILICON BRIDGE [patent_app_type] => utility [patent_app_number] => 16/632714 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16632714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/632714
ACTIVE SILICON BRIDGE Sep 12, 2017 Abandoned
Array ( [id] => 12778528 [patent_doc_number] => 20180151344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES [patent_app_type] => utility [patent_app_number] => 15/703241 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703241 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703241
Si precursors for deposition of SiN at low temperatures Sep 12, 2017 Issued
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