
Bitew A. Dinke
Examiner (ID: 17355, Phone: (571)272-0534 , Office: P/2823 )
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2812, 2896, 2823, 2826 |
| Total Applications | 880 |
| Issued Applications | 575 |
| Pending Applications | 103 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12181622
[patent_doc_number] => 20180040558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/247948
[patent_app_country] => US
[patent_app_date] => 2016-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5391
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247948
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/247948 | Semiconductor device and method of fabricating the same | Aug 25, 2016 | Issued |
Array
(
[id] => 13754725
[patent_doc_number] => 10170314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Pulsed laser anneal process for transistor with partial melt of a raised source-drain
[patent_app_type] => utility
[patent_app_number] => 15/246468
[patent_app_country] => US
[patent_app_date] => 2016-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/246468 | Pulsed laser anneal process for transistor with partial melt of a raised source-drain | Aug 23, 2016 | Issued |
Array
(
[id] => 11475620
[patent_doc_number] => 20170062403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/238912
[patent_app_country] => US
[patent_app_date] => 2016-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/238912 | Semiconductor device | Aug 16, 2016 | Issued |
Array
(
[id] => 12215015
[patent_doc_number] => 09911832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-06
[patent_title] => 'Method to improve gate dielectric quality for FinFET'
[patent_app_type] => utility
[patent_app_number] => 15/236331
[patent_app_country] => US
[patent_app_date] => 2016-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4200
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236331
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/236331 | Method to improve gate dielectric quality for FinFET | Aug 11, 2016 | Issued |
Array
(
[id] => 11475808
[patent_doc_number] => 20170062591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'METHOD TO ENHANCE 14NM FINFET DEVICE PERFORMANCE BY THE STI OXIDE LOSS CONTROL'
[patent_app_type] => utility
[patent_app_number] => 15/236344
[patent_app_country] => US
[patent_app_date] => 2016-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236344
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/236344 | Method to enhance FinFET device performance with channel stop layer depth control | Aug 11, 2016 | Issued |
Array
(
[id] => 12936277
[patent_doc_number] => 09831324
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-28
[patent_title] => Self-aligned inner-spacer replacement process using implantation
[patent_app_type] => utility
[patent_app_number] => 15/235357
[patent_app_country] => US
[patent_app_date] => 2016-08-12
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235357
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/235357 | Self-aligned inner-spacer replacement process using implantation | Aug 11, 2016 | Issued |
Array
(
[id] => 12102316
[patent_doc_number] => 09859418
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-02
[patent_title] => 'Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 15/234520
[patent_app_country] => US
[patent_app_date] => 2016-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 11645
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234520
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/234520 | Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit | Aug 10, 2016 | Issued |
Array
(
[id] => 12047422
[patent_doc_number] => 09825031
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-21
[patent_title] => 'Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices'
[patent_app_type] => utility
[patent_app_number] => 15/229292
[patent_app_country] => US
[patent_app_date] => 2016-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3917
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229292
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/229292 | Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices | Aug 4, 2016 | Issued |
Array
(
[id] => 12102317
[patent_doc_number] => 09859419
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-02
[patent_title] => 'Stacked-gate super-junction MOSFET'
[patent_app_type] => utility
[patent_app_number] => 15/224835
[patent_app_country] => US
[patent_app_date] => 2016-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224835
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/224835 | Stacked-gate super-junction MOSFET | Jul 31, 2016 | Issued |
Array
(
[id] => 11544804
[patent_doc_number] => 20170098629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-06
[patent_title] => 'STACKED FAN-OUT PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 15/218379
[patent_app_country] => US
[patent_app_date] => 2016-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218379
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/218379 | STACKED FAN-OUT PACKAGE STRUCTURE | Jul 24, 2016 | Abandoned |
Array
(
[id] => 11904311
[patent_doc_number] => 09773751
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-09-26
[patent_title] => 'Via and trench filling using injection molded soldering'
[patent_app_type] => utility
[patent_app_number] => 15/214935
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/214935 | Via and trench filling using injection molded soldering | Jul 19, 2016 | Issued |
Array
(
[id] => 12104847
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[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-09
[patent_title] => 'Via and trench filling using injection molded soldering'
[patent_app_type] => utility
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Array
(
[id] => 11890951
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[patent_title] => 'Via and trench filling using injection molded soldering'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/214914 | Via and trench filling using injection molded soldering | Jul 19, 2016 | Issued |
Array
(
[id] => 11925622
[patent_doc_number] => 09793211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-17
[patent_title] => 'Dual power structure with connection pins'
[patent_app_type] => utility
[patent_app_number] => 15/213486
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/213486 | Dual power structure with connection pins | Jul 18, 2016 | Issued |
Array
(
[id] => 11439268
[patent_doc_number] => 20170040289
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[patent_issue_date] => 2017-02-09
[patent_title] => 'SEMICONDUCTOR PACKAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/213392 | SEMICONDUCTOR PACKAGE | Jul 17, 2016 | Abandoned |
Array
(
[id] => 11132357
[patent_doc_number] => 20160329333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING STRAIN-RELAXED BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/212367 | SEMICONDUCTOR DEVICE HAVING STRAIN-RELAXED BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME | Jul 17, 2016 | Abandoned |
Array
(
[id] => 11403392
[patent_doc_number] => 20170023930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'HOUSEHOLD APPLIANCE CLOSURE ELEMENT WITH TOUCH INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 15/210458
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[patent_app_date] => 2016-07-14
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210458
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/210458 | Household appliance closure element with touch interface | Jul 13, 2016 | Issued |
Array
(
[id] => 12047398
[patent_doc_number] => 09825007
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-21
[patent_title] => 'Chip package structure with molding layer and method for forming the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208764 | Chip package structure with molding layer and method for forming the same | Jul 12, 2016 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/206417 | Electronic component device | Jul 10, 2016 | Issued |