Search

Bitew A. Dinke

Examiner (ID: 17355, Phone: (571)272-0534 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2812, 2896, 2823, 2826
Total Applications
880
Issued Applications
575
Pending Applications
103
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9542609 [patent_doc_number] => 20140167255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'PACKAGE STRUCTURE AND PACKAGE METHOD' [patent_app_type] => utility [patent_app_number] => 14/079377 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5167 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/079377
PACKAGE STRUCTURE AND PACKAGE METHOD Nov 12, 2013 Abandoned
Array ( [id] => 9474397 [patent_doc_number] => 20140131860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/078623 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7118 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/078623
Semiconductor device, semiconductor integrated circuit device, and electronic device Nov 12, 2013 Issued
Array ( [id] => 10964817 [patent_doc_number] => 20140367850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'STACKED PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/077771 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077771
STACKED PACKAGE AND METHOD OF FABRICATING THE SAME Nov 11, 2013 Abandoned
Array ( [id] => 9488413 [patent_doc_number] => 20140138819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING TSV AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/074573 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074573 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074573
SEMICONDUCTOR DEVICE INCLUDING TSV AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME Nov 6, 2013 Abandoned
Array ( [id] => 9460497 [patent_doc_number] => 20140124923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING A STAGGERED PAD WIRING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/072993 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/072993
SEMICONDUCTOR DEVICES HAVING A STAGGERED PAD WIRING STRUCTURE Nov 5, 2013 Abandoned
Array ( [id] => 9534589 [patent_doc_number] => 20140159235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'ELECTRONIC COMPONENT, ELECTRONIC APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHOD OF THE ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/073144 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16091 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073144 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073144
ELECTRONIC COMPONENT, ELECTRONIC APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHOD OF THE ELECTRONIC APPARATUS Nov 5, 2013 Abandoned
Array ( [id] => 9566013 [patent_doc_number] => 20140183726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'PACKAGE SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND PACKAGE ON PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/073309 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9076 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073309
PACKAGE SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND PACKAGE ON PACKAGE SUBSTRATE Nov 5, 2013 Abandoned
Array ( [id] => 10238270 [patent_doc_number] => 20150123265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SOLDER BUMP ARRANGEMENTS FOR LARGE AREA ANALOG CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 14/071865 [patent_app_country] => US [patent_app_date] => 2013-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9739 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071865 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/071865
Solder bump arrangements for large area analog circuitry Nov 4, 2013 Issued
Array ( [id] => 10924111 [patent_doc_number] => 20140327132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'TSV Backside Reveal Structure and Exposing Process' [patent_app_type] => utility [patent_app_number] => 14/071453 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5567 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071453 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/071453
TSV Backside Reveal Structure and Exposing Process Nov 3, 2013 Abandoned
Array ( [id] => 9737813 [patent_doc_number] => 20140273531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES' [patent_app_type] => utility [patent_app_number] => 14/062328 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062328
Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES Oct 23, 2013 Abandoned
Array ( [id] => 9508836 [patent_doc_number] => 20140145327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/060913 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060913 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/060913
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Oct 22, 2013 Abandoned
Array ( [id] => 10223642 [patent_doc_number] => 20150108635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/061615 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5245 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061615
Semiconductor structure and manufacturing method thereof Oct 22, 2013 Issued
Array ( [id] => 10223596 [patent_doc_number] => 20150108589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/059480 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5596 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059480 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059480
Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors Oct 21, 2013 Issued
Array ( [id] => 11286474 [patent_doc_number] => 09502333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Semiconductor device having conductive vias' [patent_app_type] => utility [patent_app_number] => 14/056230 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3882 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056230 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056230
Semiconductor device having conductive vias Oct 16, 2013 Issued
Array ( [id] => 9905919 [patent_doc_number] => 20150061119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'CIRCUIT SUBSTRATE, SEMICONDUTOR PACKAGE STRUCTURE AND PROCESS FOR FABRICATING A CIRCUIT SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/054850 [patent_app_country] => US [patent_app_date] => 2013-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/054850
Circuit substrate and semicondutor package structure Oct 15, 2013 Issued
Array ( [id] => 11781911 [patent_doc_number] => 09391112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/038516 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 12415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038516
Semiconductor apparatus Sep 25, 2013 Issued
Array ( [id] => 9728790 [patent_doc_number] => 20140264497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/037253 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1929 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037253
SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS Sep 24, 2013 Abandoned
Array ( [id] => 9729039 [patent_doc_number] => 20140264746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SELF ALIGNED CAPACITOR FABRICATION' [patent_app_type] => utility [patent_app_number] => 14/037334 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3006 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037334
Self aligned capacitor fabrication Sep 24, 2013 Issued
Array ( [id] => 10515412 [patent_doc_number] => 09242444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Method of fabricating a composite structure with a stable bonding layer of oxide' [patent_app_type] => utility [patent_app_number] => 14/031498 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5715 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/031498
Method of fabricating a composite structure with a stable bonding layer of oxide Sep 18, 2013 Issued
Array ( [id] => 11221803 [patent_doc_number] => 09450150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Nitride semiconductor light-emitting element' [patent_app_type] => utility [patent_app_number] => 14/400625 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6606 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14400625 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/400625
Nitride semiconductor light-emitting element Sep 4, 2013 Issued
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