Search

Blaine R Copenheaver

Supervisory Patent Examiner (ID: 13911, Phone: (571)272-1156 , Office: P/3901 )

Most Active Art Unit
1700
Art Unit(s)
1314, 1771, 1754, 1724, 1732, 1504, 1722, 1700
Total Applications
66438
Issued Applications
398
Pending Applications
64910
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18846801 [patent_doc_number] => 20230409205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 18/339812 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339812 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339812
HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE Jun 21, 2023 Pending
Array ( [id] => 18584636 [patent_doc_number] => 20230266900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MULTI-MODE NVME OVER FABRICS DEVICE FOR SUPPORTING CAN (CONTROLLER AREA NETWORK) BUS OR SMBUS INTERFACE [patent_app_type] => utility [patent_app_number] => 18/139260 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139260
MULTI-MODE NVME OVER FABRICS DEVICE FOR SUPPORTING CAN (CONTROLLER AREA NETWORK) BUS OR SMBUS INTERFACE Apr 24, 2023 Pending
Array ( [id] => 18499158 [patent_doc_number] => 20230221899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => DIRECT MEMORY ACCESS DATA PATH FOR RAID STORAGE [patent_app_type] => utility [patent_app_number] => 18/174487 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174487 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174487
DIRECT MEMORY ACCESS DATA PATH FOR RAID STORAGE Feb 23, 2023 Pending
Array ( [id] => 18438440 [patent_doc_number] => 20230185735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN [patent_app_type] => utility [patent_app_number] => 18/105727 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105727
Packet processing system, method and device utilizing a port client chain Feb 2, 2023 Issued
Array ( [id] => 18438439 [patent_doc_number] => 20230185734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN [patent_app_type] => utility [patent_app_number] => 18/105700 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105700
Packet processing system, method and device utilizing a port client chain Feb 2, 2023 Issued
Array ( [id] => 18438442 [patent_doc_number] => 20230185737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN [patent_app_type] => utility [patent_app_number] => 18/105751 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105751 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105751
Packet processing system, method and device utilizing a port client chain Feb 2, 2023 Issued
Array ( [id] => 18438441 [patent_doc_number] => 20230185736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN [patent_app_type] => utility [patent_app_number] => 18/105741 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105741
PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN Feb 2, 2023 Pending
Array ( [id] => 18422508 [patent_doc_number] => 20230176972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => MEMORY PERFORMANCE DURING PROGRAM SUSPEND PROTOCOL [patent_app_type] => utility [patent_app_number] => 18/104897 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104897
MEMORY PERFORMANCE DURING PROGRAM SUSPEND PROTOCOL Feb 1, 2023 Pending
Array ( [id] => 18407650 [patent_doc_number] => 20230169003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Scalable Cache Coherency Protocol [patent_app_type] => utility [patent_app_number] => 18/160575 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160575
Scalable cache coherency protocol Jan 26, 2023 Issued
Array ( [id] => 18351488 [patent_doc_number] => 20230139599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => STACKED MEMORY AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/146996 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146996 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146996
STACKED MEMORY AND STORAGE SYSTEM Dec 26, 2022 Pending
Array ( [id] => 18325795 [patent_doc_number] => 20230123923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHODS AND SYSTEMS FOR DATA RESYNCHRONIZATION IN A REPLICATION ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/068774 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068774
METHODS AND SYSTEMS FOR DATA RESYNCHRONIZATION IN A REPLICATION ENVIRONMENT Dec 19, 2022 Pending
Array ( [id] => 19061688 [patent_doc_number] => 11940922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => ISA extension for high-bandwidth memory [patent_app_type] => utility [patent_app_number] => 18/081488 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5045 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081488
ISA extension for high-bandwidth memory Dec 13, 2022 Issued
Array ( [id] => 18256358 [patent_doc_number] => 20230083397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => Scalable Cache Coherency Protocol [patent_app_type] => utility [patent_app_number] => 18/058105 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058105
Scalable cache coherency protocol Nov 21, 2022 Issued
Array ( [id] => 18360583 [patent_doc_number] => 20230142174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MEMORY SYSTEM USING HOST MEMORY BUFFER AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/979554 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979554
MEMORY SYSTEM USING HOST MEMORY BUFFER AND OPERATION METHOD THEREOF Nov 1, 2022 Pending
Array ( [id] => 18965810 [patent_doc_number] => 11899574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches [patent_app_type] => utility [patent_app_number] => 17/965542 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/965542
L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches Oct 12, 2022 Issued
Array ( [id] => 18989607 [patent_doc_number] => 20240061576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => HOST RATE ADJUSTMENT USING FREE SPACE VALUES [patent_app_type] => utility [patent_app_number] => 17/961050 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961050
HOST RATE ADJUSTMENT USING FREE SPACE VALUES Oct 5, 2022 Pending
Array ( [id] => 18694667 [patent_doc_number] => 20230325083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHOD FOR DELETING DATA ACCUMULATED BY AOI PROCESSES IN AIO, DATA DELETION DEVICE, DEVICE USING METHOD, AND NON-TRANSITORY STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/895492 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895492
METHOD FOR DELETING DATA ACCUMULATED BY AOI PROCESSES IN AIO, DATA DELETION DEVICE, DEVICE USING METHOD, AND NON-TRANSITORY STORAGE MEDIUM Aug 24, 2022 Pending
Array ( [id] => 18079588 [patent_doc_number] => 20220405200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => COMPRESSED DATA MANAGEMENT IN ZONES [patent_app_type] => utility [patent_app_number] => 17/894857 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894857
COMPRESSED DATA MANAGEMENT IN ZONES Aug 23, 2022 Pending
Array ( [id] => 18182447 [patent_doc_number] => 20230043177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => BIAS CONTROL FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/890032 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890032
Bias control for a memory device Aug 16, 2022 Issued
Array ( [id] => 18904536 [patent_doc_number] => 20240020021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DATA RETRY-READ METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT ELEMENT [patent_app_type] => utility [patent_app_number] => 17/886416 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886416
DATA RETRY-READ METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT ELEMENT Aug 10, 2022 Pending
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