Search

Blaine R Copenheaver

Supervisory Patent Examiner (ID: 12523, Phone: (571)272-1156 , Office: P/3901 )

Most Active Art Unit
1700
Art Unit(s)
1700, 1722, 1314, 1754, 1724, 1504, 1771, 1732
Total Applications
66441
Issued Applications
398
Pending Applications
64916
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1156135 [patent_doc_number] => 06762095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Method of fabricating flash memory' [patent_app_type] => B1 [patent_app_number] => 10/250007 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3076 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762095.pdf [firstpage_image] =>[orig_patent_app_number] => 10250007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/250007
Method of fabricating flash memory May 27, 2003 Issued
Array ( [id] => 1126595 [patent_doc_number] => 06790739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Structure and methods for process integration in vertical DRAM cell fabrication' [patent_app_type] => B2 [patent_app_number] => 10/249997 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790739.pdf [firstpage_image] =>[orig_patent_app_number] => 10249997 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249997
Structure and methods for process integration in vertical DRAM cell fabrication May 26, 2003 Issued
Array ( [id] => 7313608 [patent_doc_number] => 20040033657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Method for fabricating memory unit with T-shaped gate' [patent_app_type] => new [patent_app_number] => 10/435447 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 3396 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033657.pdf [firstpage_image] =>[orig_patent_app_number] => 10435447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435447
Method for fabricating memory unit with T-shaped gate May 8, 2003 Issued
Array ( [id] => 7304870 [patent_doc_number] => 20040140505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Electrostatic discharge device protection structure' [patent_app_type] => new [patent_app_number] => 10/348387 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140505.pdf [firstpage_image] =>[orig_patent_app_number] => 10348387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348387
Electrostatic discharge device protection structure Jan 20, 2003 Issued
Array ( [id] => 1130272 [patent_doc_number] => 06787400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Electrostatic discharge protection device having a graded junction and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 10/346668 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5623 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787400.pdf [firstpage_image] =>[orig_patent_app_number] => 10346668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346668
Electrostatic discharge protection device having a graded junction and method for forming the same Jan 15, 2003 Issued
Array ( [id] => 7360054 [patent_doc_number] => 20040014322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method for forming patterns of a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/331527 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3163 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014322.pdf [firstpage_image] =>[orig_patent_app_number] => 10331527 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331527
Method for forming patterns of a semiconductor device Dec 29, 2002 Issued
Array ( [id] => 6659684 [patent_doc_number] => 20030134472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method of manufacturing a flash memory cell' [patent_app_type] => new [patent_app_number] => 10/310387 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4615 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134472.pdf [firstpage_image] =>[orig_patent_app_number] => 10310387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310387
Method of manufacturing a flash memory cell Dec 4, 2002 Issued
Array ( [id] => 1192881 [patent_doc_number] => 06730530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Semiconductor light emitting element formed on a clear or translucent substrate' [patent_app_type] => B2 [patent_app_number] => 10/303461 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2428 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730530.pdf [firstpage_image] =>[orig_patent_app_number] => 10303461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303461
Semiconductor light emitting element formed on a clear or translucent substrate Nov 24, 2002 Issued
Array ( [id] => 1149555 [patent_doc_number] => 06770556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method of depositing a low dielectric with organo silane' [patent_app_type] => B2 [patent_app_number] => 10/301019 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 8155 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770556.pdf [firstpage_image] =>[orig_patent_app_number] => 10301019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301019
Method of depositing a low dielectric with organo silane Nov 20, 2002 Issued
Array ( [id] => 1153005 [patent_doc_number] => 06770927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Structures comprising transistor gates' [patent_app_type] => B2 [patent_app_number] => 10/301268 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770927.pdf [firstpage_image] =>[orig_patent_app_number] => 10301268 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301268
Structures comprising transistor gates Nov 19, 2002 Issued
Array ( [id] => 6783101 [patent_doc_number] => 20030064548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Panel stacking of BGA devices to form three-dimensional modules' [patent_app_type] => new [patent_app_number] => 10/290994 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7735 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20030064548.pdf [firstpage_image] =>[orig_patent_app_number] => 10290994 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290994
Panel stacking of BGA devices to form three-dimensional modules Nov 7, 2002 Abandoned
Array ( [id] => 6781133 [patent_doc_number] => 20030062580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Spin-valve transistor' [patent_app_type] => new [patent_app_number] => 10/287584 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4435 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062580.pdf [firstpage_image] =>[orig_patent_app_number] => 10287584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287584
Spin-valve transistor Nov 4, 2002 Abandoned
10/191368 Light emitting semiconductor device using nitrogen-group III compound Jun 25, 2002 Abandoned
Array ( [id] => 1175421 [patent_doc_number] => 06746956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Hermetic seal for silicon die with metal feed through structure' [patent_app_type] => B1 [patent_app_number] => 10/170506 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 4325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746956.pdf [firstpage_image] =>[orig_patent_app_number] => 10170506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/170506
Hermetic seal for silicon die with metal feed through structure Jun 12, 2002 Issued
Array ( [id] => 1332251 [patent_doc_number] => 06596587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Shallow junction EEPROM device and process for fabricating the device' [patent_app_type] => B1 [patent_app_number] => 10/162337 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2954 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596587.pdf [firstpage_image] =>[orig_patent_app_number] => 10162337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162337
Shallow junction EEPROM device and process for fabricating the device Jun 2, 2002 Issued
Array ( [id] => 6803414 [patent_doc_number] => 20030230808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'High aspect ratio fill method and resulting structure' [patent_app_type] => new [patent_app_number] => 10/156097 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3430 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20030230808.pdf [firstpage_image] =>[orig_patent_app_number] => 10156097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156097
High aspect ratio fill method and resulting structure May 28, 2002 Issued
Array ( [id] => 6694876 [patent_doc_number] => 20030107070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/125427 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6448 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107070.pdf [firstpage_image] =>[orig_patent_app_number] => 10125427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125427
Semiconductor device and method of fabricating the same Apr 18, 2002 Issued
Array ( [id] => 1123245 [patent_doc_number] => 06794211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Light emitting diode and method of fabricating thereof' [patent_app_type] => B2 [patent_app_number] => 10/101800 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2907 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794211.pdf [firstpage_image] =>[orig_patent_app_number] => 10101800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/101800
Light emitting diode and method of fabricating thereof Mar 19, 2002 Issued
Array ( [id] => 6306661 [patent_doc_number] => 20020094627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Electrostatic discharge protection device having a graded junction and method for forming the same' [patent_app_type] => new [patent_app_number] => 10/095640 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5601 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094627.pdf [firstpage_image] =>[orig_patent_app_number] => 10095640 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/095640
Electrostatic discharge protection device having a graded junction and method for forming the same Mar 10, 2002 Issued
Array ( [id] => 6076024 [patent_doc_number] => 20020079546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (\"ESD\") protection' [patent_app_type] => new [patent_app_number] => 10/020687 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5068 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079546.pdf [firstpage_image] =>[orig_patent_app_number] => 10020687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020687
Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD) protection Dec 13, 2001 Issued
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