Search

Blair M. Johnson

Examiner (ID: 4242, Phone: (571)272-6830 , Office: P/3634 )

Most Active Art Unit
3634
Art Unit(s)
3634, 3505, 3623, 3509
Total Applications
3198
Issued Applications
2330
Pending Applications
84
Abandoned Applications
790

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18445421 [patent_doc_number] => 11680984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-20 [patent_title] => Control data registers for scan testing [patent_app_type] => utility [patent_app_number] => 17/683126 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683126
Control data registers for scan testing Feb 27, 2022 Issued
Array ( [id] => 18584126 [patent_doc_number] => 20230266388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => PROGRAMMABLE SCAN CHAIN DEBUG TECHNIQUE [patent_app_type] => utility [patent_app_number] => 17/679686 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679686
Programmable scan chain debug technique Feb 23, 2022 Issued
Array ( [id] => 19138536 [patent_doc_number] => 11973517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Reconfigurable FEC [patent_app_type] => utility [patent_app_number] => 17/679606 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5263 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679606
Reconfigurable FEC Feb 23, 2022 Issued
Array ( [id] => 18479320 [patent_doc_number] => 11693054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Computer-readable recording medium storing analysis program, analysis method, and analysis device [patent_app_type] => utility [patent_app_number] => 17/676886 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10804 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676886
Computer-readable recording medium storing analysis program, analysis method, and analysis device Feb 21, 2022 Issued
Array ( [id] => 18154157 [patent_doc_number] => 11567132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Scan apparatus capable of fault diagnosis and scan chain fault diagnosis method [patent_app_type] => utility [patent_app_number] => 17/673075 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5410 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673075
Scan apparatus capable of fault diagnosis and scan chain fault diagnosis method Feb 15, 2022 Issued
Array ( [id] => 18568378 [patent_doc_number] => 20230258714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => ICG TEST COVERAGE WITH NO TIMING OVERHEAD [patent_app_type] => utility [patent_app_number] => 17/672527 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672527
ICG TEST COVERAGE WITH NO TIMING OVERHEAD Feb 14, 2022 Abandoned
Array ( [id] => 20132790 [patent_doc_number] => 12375108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Information bit determination method and mapping generation method for polar-coded modulation, and device [patent_app_type] => utility [patent_app_number] => 18/264625 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/264625
Information bit determination method and mapping generation method for polar-coded modulation, and device Feb 9, 2022 Issued
Array ( [id] => 18605939 [patent_doc_number] => 11747398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Scan chain circuit and corresponding method [patent_app_type] => utility [patent_app_number] => 17/665247 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665247
Scan chain circuit and corresponding method Feb 3, 2022 Issued
Array ( [id] => 18667604 [patent_doc_number] => 11774496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof [patent_app_type] => utility [patent_app_number] => 17/578526 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 6486 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578526
Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof Jan 18, 2022 Issued
Array ( [id] => 18486237 [patent_doc_number] => 20230213580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SIGNAL TOGGLING DETECTION AND CORRECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/647076 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647076
Signal toggling detection and correction circuit Jan 4, 2022 Issued
Array ( [id] => 18486946 [patent_doc_number] => 20230214292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => PROGRAMMABLE SIGNAL AGGREGATOR [patent_app_type] => utility [patent_app_number] => 17/567540 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567540
Programmable signal aggregator Jan 2, 2022 Issued
Array ( [id] => 18247642 [patent_doc_number] => 11604221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Clock shaper circuit for transition fault testing [patent_app_type] => utility [patent_app_number] => 17/566190 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566190
Clock shaper circuit for transition fault testing Dec 29, 2021 Issued
Array ( [id] => 17552515 [patent_doc_number] => 20220123858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/564531 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564531
Method and apparatus for channel encoding/decoding in a communication or broadcasting system Dec 28, 2021 Issued
Array ( [id] => 17534742 [patent_doc_number] => 20220113351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE [patent_app_type] => utility [patent_app_number] => 17/559444 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559444
Wafer scale testing using a 2 signal JTAG interface Dec 21, 2021 Issued
Array ( [id] => 18175662 [patent_doc_number] => 11575388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Method and device in UE and base station for channel coding [patent_app_type] => utility [patent_app_number] => 17/558625 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 457 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558625
Method and device in UE and base station for channel coding Dec 21, 2021 Issued
Array ( [id] => 17534741 [patent_doc_number] => 20220113350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/559322 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559322
Segmented row repair for programmable logic devices Dec 21, 2021 Issued
Array ( [id] => 18248108 [patent_doc_number] => 11604696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Field programmable gate array (FPGA) for improving reliability of key configuration bitstream by reusing buffer memory [patent_app_type] => utility [patent_app_number] => 17/645314 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3629 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645314
Field programmable gate array (FPGA) for improving reliability of key configuration bitstream by reusing buffer memory Dec 20, 2021 Issued
Array ( [id] => 18247644 [patent_doc_number] => 11604223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Clock control system for scan chains [patent_app_type] => utility [patent_app_number] => 17/644605 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15655 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644605
Clock control system for scan chains Dec 15, 2021 Issued
Array ( [id] => 17839001 [patent_doc_number] => 20220276306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND DSP/FPGA [patent_app_type] => utility [patent_app_number] => 17/626823 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626823
COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND DSP/FPGA Dec 15, 2021 Abandoned
Array ( [id] => 18118593 [patent_doc_number] => 11549983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => 3D tap and scan port architectures [patent_app_type] => utility [patent_app_number] => 17/551406 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 10174 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551406
3D tap and scan port architectures Dec 14, 2021 Issued
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